IO PIN STATUS during FPGA Reconfiguration

[SK_VA]

Hi ,

During FPGA reconfiguration what is the status of FPGA I/O pins. Will the I/Os toggle or retain the state driven by the previous image.

How the I/O transition takes place during reconfiguration.

[AminT_Intel]

Hello,

May I know which Intel FPGA devices are you asking about? This information will help me answering your questions better. 

[SK_VA]

For Max 10 FPGA

[AminT_Intel]

Hello, 

For your questions it will depends on your IO configurations that you set. You may refer to this document for more details: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_gpio.pdf

I hope this helps. 

[MLars19]

Hi

I'm searching for this information regarding Cyclone V.

It seems hard to find the information regarding the state of the IOs when you trigger a reconfiguration in the altremote ip.

Thanks

Magnus