I have a strange problem with a tristate buffer at MAX 10:
I am using symbol based design and did not find an enable buffer in place into the toplevel. Therefore I created one myself the common way: if (enable) then IOPAD <= output; else IOPAD = 'Z'; end if; Signal IOPAD is directly connected to a tristate buffer symbol ( <> ) . The output report shows a bidirectional port for this signal, so it seems to be ok. Also a "fast Output enable" constraint is accepted. I am observing the ENABLE as well as the OUTPUT and the INPUT of the signal in SignalTAP and can regularly see the output's values at the input when ENABLE is high. But sometimes (not always !) the wire seems to be held low, while ENABLE is low, although there is a 10k pullup resistor on the board. According to the states, the pullup seems to operate, since I can observe the signal slowly rising in the oscilloscope when the enable to low. In the "strange cases" the INPUT is LOW and seems to be hard pulled down by an output. The target device should not be the reason for this. It appears as if the output memorizes the latest state of the internal output signal, when enable goes low. The VHDL cirtuitry runs fine in simulation and operates well in another design. I am unsure what the synthesis migh have produced from within the description. Any idea how I can verify this?