IO cell registers

[Altera_Forum]

I had a a few general question about using IOE registers. From the data sheet most FPGA have built int IO elements which allow fast setup and output times with respect to the clock. On my designs I noticed by default Quartus will not use the IOE registers. Instead it uses register in the core. 

 So my 1st question, is it correct to assume Quartus perfers not to use IOE registers? Why?   Another question, I tried to use Fast Input Register and Fast Output Enable Register, but the fitter does not like it and reports the setting is ignored. Why is this? Can I force the use of the register?

[Altera_Forum]

--- Quote Start ---   So my 1st question, is it correct to assume Quartus perfers not to use IOE registers? Why?    --- Quote End ---  Quartus will only do enough work to meet your design constraints. If you do not give it any constraints, then it does not do much work :)  If you provide a TimeQuest timing constraint that can only be met by using the IOE registers, then it will use them.    --- Quote Start ---   Another question, I tried to use Fast Input Register and Fast Output Enable Register, but the fitter does not like it and reports the setting is ignored. Why is this? Can I force the use of the register?  --- Quote End ---  If your signal is an input or output-only, then an output enable constraint would be ignored. That constraint would only apply to a tri-state output, or bidirectional signal. 'Ignored' may just reflect an error in your constraint.  If you set a valid constraint, Quartus will implement it, so yes you can force the use of the IOE registers.  See this thread for an example; http://www.alteraforum.com/forum/showthread.php?t=31457  Cheers, Dave