Reducing Rise Time of Max V

[Altera_Forum]

I have a Max V (570Z) which I've programmed as a large (100 bit) Paralell In Serial Out shift register. I communicate with the CPLD via SPI. 

 When I shift the data out, I notice significant ringing on the waveform. This requires me to include some resistance between the CPLD and the MCU on the MISO line.   However, I was wondering, is it possible to reduce the rise time of the CPLD via programming?

[Altera_Forum]

The appearance of ringing at the output of any digital device can be significantly affected by how well you're doing the probing. Before trying to "fix" the ringing you should make sure that it's real. The length of the ground lead on your scope probe should be a maximum of 1", and preferably less. The faster the edge rate of the signal, the shorter the ground lead needs to be. 

 Also, try "probing ground" with your oscilloscope. Put both the ground lead and the probe tip on a ground point near the swtiching output of the CPLD. Do you see lots of ringing there? If so this is clearly an artifact of the probing. This calls into question any ringing that you see on the output of the CPLD.  Finally, some ringing on the MISO line may be OK if the CLOCK line is clean.

[Altera_Forum]

Setting low current strength and possibly slow slew rate in pin options is another way to improve signal quality of I/Os that don't need highest speed.