Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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IOPLL in normal mode，output edge and input edge are not aligned

jli125
Beginner
‎02-02-2019 08:04 AM
1,171 Views

The device is Arria 10. IOPLL input clk freq is 100M，output0 is 100M and output1 is 800M. Output0 is used as an internal clock. In the image，this is the SignalTap screenshot，and sampling clock is ouput1（800M），Why the two signals are not aligned？

1.jpg

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Rahul_S_Intel1
Employee
‎02-26-2019 06:01 AM
392 Views
Hi , Kinldy check, is there any phase sift is provided in the PLL IP. Mostly this will happens because of phase shift. Regards, Rs
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