ISP1761 and Altera DMA

[Altera_Forum]

Hi all,

I use ISP1761 USB Controller for PC <--> FPGA communication

So to adapt USB PIO to Avalon interface :

--! SO_ISP1761 entity brief description

entity SO_ISP1761 is port(

-- Avalon interface 

av_cs_n : in std_logic; --! chip select from avalon interface

av_write_n : in std_logic; --! write enable from avalon interface

av_read_n : in std_logic; --! read enable from avalon interface

av_address : in std_logic_vector(17 downto 0); --! address from avalon interface

av_writedata : in std_logic_vector(31 downto 0); --! data to usb

av_readdata : out std_logic_vector(31 downto 0); --! data from usb

av_hc_irq : out std_logic; --! Host Controller to avalon interface irq

av_dc_irq : out std_logic; --! Peripheral Controller to avalon interface irq

av_dc_readdata : out std_logic_vector(31 downto 0); --! dummy for irq slave 

-- interface with IPS1761 module 

dc_irq : in std_logic; --! Peripheral Controller interrupt signal 

hc_irq : in std_logic; --! Host Controller interrupt signal

dc_dreq : in std_logic; --! DMA controller request for the Peripheral Controller

hc_dreq : in std_logic; --! DMA controller request for Host Controller

usb_d : inout std_logic_vector(31 downto 0); --! data bidirectional pads

dc_dack : out std_logic; --! Peripheral Controller DMA request acknowledgment

hc_dack : out std_logic; --! Host Controller DMA request acknowledgment

usb_a : out std_logic_vector(17 downto 1); --! address

usb_cs_n : out std_logic; --! chip select assertion indicates the ISP1761 being accessed; active LOW

usb_rd_n : out std_logic; --! read enable; active LOW

usb_wr_n : out std_logic --! write enable; active LOW

);

end entity SO_ISP1761;

--! @brief Architure definition 

--! Adapt extern usb interface to avalon interface 

architecture rtl of SO_ISP1761 is 

begin

usb_a <= av_address(17 downto 1);

usb_d <= av_writedata when av_cs_n = '0' and av_read_n ='1' 

else (others => 'Z') ; 

av_readdata <= usb_d when av_cs_n = '0' and av_read_n ='0' and av_write_n ='1' 

else (others => 'Z') ; 

usb_cs_n <= av_cs_n; 

usb_wr_n <= av_write_n;

usb_rd_n <= av_read_n;

av_hc_irq <= hc_irq; 

av_dc_irq <= dc_irq;

end architecture rtl;

TCL file :