If generate statement in vhdl for enabling and disabling hardware

Altera_Forum · ‎03-09-2012

I want to enable or disable logic using en_logic from external environment

en_logic is defined as a std_logic input signal from external environment

not_gen_logic : if (en_logic = '0') generate

in1 <= rx_inp1;

in2 <= rx_inp2;

in3 <= rx_inp3;

in4<= rx_inp4;

end generate;

gen_logic : if (en_logic = '1') generate

in1 <= rx_inp5;

in2 <= rx_inp6;

in3 <= rx_inp7;

in4 <= rx_inp8;

end generate;

but strangely i see an error pointed by quartus

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"Error 10807 VHDL error : condition in generation scheme must be a static expression"

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but if i define en_logic as a constant i dont see this error

Please guide me how can we use if generate statement to enable or disable a desired logic

Altera_Forum · ‎03-09-2012

Generate statements are used to create different static implementations.

What you are really after is using en_logic as a multiplexer control.


in(1 to 4) <= rx_inp(1 to 4) when (en_logic = '0') else rx_inp(5 to 8);

Cheers,

Dave