cyclone iii altparallel_flash_loader + pfl_flash_access_granted port question

[Altera_Forum]

Does anybody know how the pfl_flash_access_granted port works on the altparallel_flash_loader mega function with a CFI/ P30 flash chip in a cyclone III. My main issue is that the Altera documentation goes over all kind of different implementations using an intermediate MAX II chip, but for cyclone III, since it can directly interface to the flash chip there is no need for the extra chip. Quartus allows the flash loader ip compiled inside a cyclone iii design but only supports pfl_flash_access_granted and pfl_access_request ports. I sure wish they would have allowed reading and writing as well. 

 Anyway my issue is I want to continue to use the altera parallel flash loader IP while also having the ability to read and write to the flash chip from my fpga design in the cyclone iii. From what I can guess Altera supports arbitration through the pfl_flash_access_granted and the request ports so it should be possible, but the documentation is fuzzy.  Cyclone III is supposed to tie DCLK configuartion pin to be the clock poin of the flash chip. When I instantiate the altera parallel flash loader IP however there is no clock port to map unlike all the other pins. So it some kind of vodoo magic mega function mapping done there.  So my 1st question is it possible to access the same clock source that drives altera parallel flash loader ip and the flash / DCLK pin?   If not, then it do I have to disable my own the clock output when the altera ip request and subsequent access is granbted?  It not clear in the doc how this is supposed to work. Anybody done this?  Thanks.