Ignored create_clock warning in C V design

[Seadog]

I have a Cyclone V design with a DDR 3 controller.  The reference clock for the DDR3 EMIF core is routed directly from a clock pin.  The .sdc file for the project has a create_clock command for that reference clock; the .sdc file for the EMIF core also has a create_clock command for the same clock (referenced as pll_ref_clk per the port name on the EMIF top level).

Quartus is giving me the following warning:

Warning (332049): Ignored create_clock at ddr3_v20_p0.sdc(264): Incorrect assignment for clock. Source node: clkinbot_p already has a clock(s) assigned to it. Use the -add option to assign multiple clocks to this node. Clock was not created or updated.

Should I:

• comment out the create_clock command in the project .sdc file
• use the -add option (not sure why I would; the clock is routed to only one place)
• ignore the warning

Thanks.

[sstrell]

You can either ignore the warning or remove your create_clock command since, as you say, the clock is not being used anywhere else in your design.  Does the tool still show the design as fully constrained?

[Seadog]

The design is fully constrained, other than the parts I purposely did not constrain (it's on an eval board with a bunch of I/Os not really being used).  And certainly the EMIF core is constrained.

[AdzimZM_Intel]

Hello,

Sorry for the delay in this topic.

You can either comment out the create_clock command in the project .sdc file or ignore the warning as has been mentioned by sstrell.

Do you have any further question?

Thanks.

Adzim

[Seadog]

No further info needed, thanks.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.