In cyclone V, at least 1 receiver channel cannot be used because CMU PLL which serves as the transmitter PLL is implemented by this resource. Is there any other way to implement the transmitter PLL so that all the receiver channels can be used? Can fPLL be used?
In the datasheet named 'Cyclone V Device Handbook, Volume 2: Transceivers', on page 30, it says:
In addition to CMU PLL, the fPLL located adjacent to the transceiver banks are available for clocking the transmitters for serial data rates up to 3.125 Gbps. Related Information: Clock Networks and PLLs in Cyclone V Devices
But after reading that 'related information', it is still unclear of how to use fPLL to drive transceiver channels.
As I understand it, you have some inquiries related to using fPLL to drive the XCVR channels in CV devices. For your information, there was previously a wiki design example in CV devices which uses fPLL to drive the Native PHY. I believe you are unable to access the wiki currently. I will send it to your email for your reference.
Please let me know if there is any concern. Thank you.
I have a look at the design. It is very helpful and solves my question. The top file is very informative.
Thank you very much!
I have one more question regarding the native PHY.
I usually do not use 'phase compensation FIFO' when I use custom PHY, because I connect the low speed parallel clock to the FPGA fabric interface clock/FPGA user-designed logic after the custom PHY. However, in the native PHY IP configuration window, I did not see a place to 'disable' the phase compensation FIFO. Is it always included? Does it do anything at all if I use the low speed parallel clock for FPGA fabric interface clock ?