How the "PARAMETER"/"localparam" in verilog mapped to hardware?

[HBhat2]

Hi,

I have a very basic question regarding RTL and FPGA.

In RTL, generally we use parameter or localparam to define the design configuration.

My question is how this "PARAMETER' or "localparam" is mapped to FPGA primitives/hardware?

( in a way similar to a simple single bit sequential logic maps into a flip flop )

With Regards,

HPB

[sstrell]

Parameters have to resolve to a fixed value at compile time, so the design is simply synthesized based on the parameter value used. If you're using a parameter, for example, to specify a bus width and you set the parameter to 8, enough resources will be used to implement an 8-bit wide bus.

#iwork4intel

[HBhat2]

@sstrell​ ,

For example, I have a header pattern to send (localparam header = 0xA5A5), I will store this as local parameter and I will assign my databus for defined interval. (data_o <= header ;). As, data_o inferred into multiple D-flip flops, my specific question is how does the header will be inferred? Whether this localparam will be stored in block RAM or by means of any other primitives ?

With Regards,

HPB

[sstrell]

For your example, it would probably be synthesized as just pull-ups and pulldowns since it's a constant value.

#iwork4intel