Indefinite states of State Machine - VHDL

[Altera_Forum]

Hi Guys, 

I would like to ask for your help...  I wrote a simple code that is identifying the rising edge of incoming signal. There are two states - every time that rising edge existing, the state machine moving the other state. In every state there are counter in order to check how many Primary Clock Cycles = 50MHz there are in every cycle of the incoming signal. Every "rise edge" of incoming signal causes to the counter to make reset and moving to another stage.  Simulation in ModelSin is successfull. When I trying to see the code behavior in Signal Tap - Quartus, I see that is works but incorrectly. Sometimes there are state x"00" when there are only two defined states - State_1 and State_2 only!!!  The Fmax of the code is something like 130MHz, I tried to reduce the Primary Clock to the 10MHz value, but it didn't help.  This occures once for sometimes. Independent of frequency of the Incoming signal(1KHz - 1MHz). Looks like when Flip-Flop missing the signal but it's impossible cause the Fmax is higher alot.   Thanks alot...  Y.

[Altera_Forum]

I suppose your incoming signal is asynchronous to your processing clock. As such it will have a different propagation delay to each register in the state machine and in the end each of the state-machine registers may see a different level, and possibly clock in an invalid transition ending up in an undefined state. 

So you have to synchronise this external input with a two-stage register chain to avoid this (and metastability) issue.

[Altera_Forum]

Hi deded84, 

 I’m not sure if I understand you right. But if your code sometimes works and sometimes not, it sounds like metastability. Is the external signal synchronized in by flip flops? You should always use synchronizers for external asynchronous signals.   Here is a good paper about this topic: http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf?gsa_pos=9&wt.oss_r=1&wt.oss=metastability    Greets Sim

[Altera_Forum]

--- Quote Start ---  I suppose your incoming signal is asynchronous to your processing clock. As such it will have a different propagation delay to each register in the state machine and in the end each of the state-machine registers may see a different level, and possibly clock in an invalid transition ending up in an undefined state. So you have to synchronise this external input with a two-stage register chain to avoid this (and metastability) issue.  --- Quote End ---    Thanks for your answer. The external incoming signal is really asynchronious with the Primary Clock...As I understand, I have to transfer the icoming signal through FF that's syncronised with Primary Clock?  I would like to add more details... The x"00" state disappear when I determine one or more states that I am not using - spare states.  Instead of x"00", I see the last state but still missing the rising edge.

[Altera_Forum]

--- Quote Start ---  Hi deded84,   I’m not sure if I understand you right. But if your code sometimes works and sometimes not, it sounds like metastability. Is the external signal synchronized in by flip flops? You should always use synchronizers for external asynchronous signals.   Here is a good paper about this topic: http://www.altera.com/literature/wp/wp-01082-quartus-ii-metastability.pdf?gsa_pos=9&wt.oss_r=1&wt.oss=metastability    Greets Sim  --- Quote End ---    Thanks for an answer, I think that you are right...will check and inform you :)

[Altera_Forum]

The passing of Incoming Signal through FF was the brilliant idea. The code is working without Indefinite states. 

Thanks to all.

[Altera_Forum]

Hi deded, 

 That sounds good. Synchronization should always be done with asynchronous external signals to avoid metastability.  Greets