Infer Large Multiplier in Stratix IV

[Altera_Forum]

Hello - looking to see if anyone else has done something like this: 

 Im using a stratix IV and in need of inferring Large Multipliers that use the DSP blocks effeciently. Using the LPM_MULT gives me an efficient compact solution, but when inferring using register retiming it doesnt use the middle pipeline register in the DSP. I am using Simulink to generate the design so ideally I would use the generated code to infer these large multipliers. This has been done successfully for Xilinx parts.  I wondered if anyone else had tried something like this. Im trying to avoid using black-boxes in the simulink model and getting HDL coder to instantiate LPM_MULTs for me. Multipliers will be anything from 30x30 to 51x51.  Regards

[Altera_Forum]

I'm sorry to say that, in my experience so far, even if you generate LPM_MULT IP using the Quartus IP generator tool and explicitly request 3 or 4 internal register delays (depending on which FPGA family you're targeting -- I've been targeting both Arria 10 and Stratix 10), if retiming is on, it appears Quartus (15.1 and 16.1 both) will pull the internal registration out, gripe at you that your DSPs aren't fully registered, and then will never put it back, even when it's failing timing miserably and has plenty of other control/reset-free registers to work with. I've looked in vain for the "put my registers back where I left them!" button to no avail. If any other users have found a way to counteract this, I'd like to know, too.