Initialise content in external memory when simulating a qsys system

[Altera_Forum]

The Qsys system I want to simulate includes external memory (DDR2) from which a large number of data will be loaded by the custom component in the system for processing. My question is how I can initialise the content in the external memory? Is it even possible to do so? Thanks!

[Altera_Forum]

It depends on the DDR2 memory model. 

 Look at the code for the memory component and see if it has initialization generics.  Look at the code and see how the memory array is implemented. If its implemented as a shared variable, you can use VHDL-2008 hierarchical access to initialize the variable.  If you have a mixed-mode simulator, and use a Verilog memory model, then you can use $readmemh to load the memory.  These various options depend on the memory model. I don't recall what Altera uses. I'd recommend creating a Qsys system with a DDR2 controller and then generating the example design. I've used this method to get the instantiation template for the memory model, and then copied that code into my own testbench.  Try some of these ideas, and if you get stuck, let me know and I can try looking to see what I have used in the past.  Cheers, Dave

[Altera_Forum]

Aside from HDL methods, you can also use the Modelsim "mem load" command to load from a file into the memory array that the model most likely instantiates.

[Altera_Forum]

--- Quote Start ---  It depends on the DDR2 memory model.  Look at the code for the memory component and see if it has initialization generics.  Look at the code and see how the memory array is implemented. If its implemented as a shared variable, you can use VHDL-2008 hierarchical access to initialize the variable.  If you have a mixed-mode simulator, and use a Verilog memory model, then you can use $readmemh to load the memory.  These various options depend on the memory model. I don't recall what Altera uses. I'd recommend creating a Qsys system with a DDR2 controller and then generating the example design. I've used this method to get the instantiation template for the memory model, and then copied that code into my own testbench.  Try some of these ideas, and if you get stuck, let me know and I can try looking to see what I have used in the past.  Cheers, Dave  --- Quote End ---    Hi Dave,  So based on your answer, is it true that there isn't a straightforward way to initialise the ddr2 memory model by using some sort of statement in either HDL file or simulator command?  I'm using Verilog memory model and Modelsim. Are you suggesting locating the memory array in the memory model and initialising it with $readmemb statement?  When generate the Qsys system I tick the option to generate a verilog test-bench, inside this test-bench I can see an "Altera ddr2 memory model for Uniphy". I guess this is the memory model you referred to. However it seems that the model is a set of wrapper files and the signal names get more and more complex and I'm not sure where the memory array is.

[Altera_Forum]

--- Quote Start ---   I'm not sure where the memory array is   --- Quote End ---   Load the design in Modelsim and then use the hierarchy display to understand how it is instantiated.  As Ted points out, Modelsim is smart enough to identify memory blocks, and you can use "mem load" to load it. Personally I like to use HDL to load the memory if I can, since they I can load the memory multiple times without having to coordinate a Modelsim Tcl script and the testbench code.  Cheers, Dave