Inout port became output

[Gianfranco9635]

Hi guys,

i'm trying to create a project based on a Bridge SPI to Avalon.  In my top entity i have a signal that is defined as "INOUT"  and that represent the I/O of my fpga (name signal is LSASBUS). My problem regards the eda netlist writer that create the file .vo. If i change something in my top entity and i compile the project, all work good. if i re-compile it, my project doesn't work. This happen because in the .vo file, the "INOUT" port became "Output" and i don't know why.  I'm using quartus lite versione 20.1.

How can i resolve? i include my top level file in vhdl.

FPGA_USER.vhd

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library lpm;

use lpm.lpm_components.all;

library altera_mf;

use altera_mf.altera_mf_components.all;

entity user is

port

(

-- Main clock inputs

mainClk : in std_logic;

slowClk : in std_logic;

-- Main reset input

reset : in std_logic;

-- MCU interface (UART, I2C)

mcuUartTx : in std_logic;

mcuUartRx : out std_logic;

mcuI2cScl : in std_logic;

mcuI2cSda : inout std_logic;

-- Logic state analyzer/stimulator

lsasBus : inout std_logic_vector( 31 downto 0 );

-- Dip switches

switches : in std_logic_vector( 7 downto 0 );

-- LEDs

leds : out std_logic_vector( 3 downto 0 );

   state_out    : out std_logic_vector(4 downto 0)

);

end user;

architecture behavioural of user is

signal clk: std_logic;

signal pllLock: std_logic;

signal lsasBusIn: std_logic_vector( 31 downto 0 );

signal lsasBusOut: std_logic_vector( 31 downto 0 );

signal lsasBusEn: std_logic_vector( 31 downto 0 ) := ( others => '0' );

signal mcuI2cDIn: std_logic;

signal mcuI2CDOut: std_logic;

signal mcuI2cEn: std_logic := '0';

signal state :  std_logic_vector(4 downto 0);

component myAltPll

PORT

(

areset : IN STD_LOGIC  := '0';

inclk0 : IN STD_LOGIC  := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC 

);

end component;

component SPI_Avalon_System

   PORT

(

    clk_clk       : in  std_logic; --   clk.clk

   reset_reset_n : in  std_logic; -- reset.reset_n

   spi_mosi      : in  std_logic; --   spi.mosi

   spi_ss        : in  std_logic; --      .ss

   spi_miso      : out std_logic;        --      .miso

   spi_sclk      : in  std_logic;  --      .sclk

         en_miso       : out std_logic;

      state         : out std_logic_vector(4 downto 0);

   ss_sys        : out std_logic

   );

   end component;

begin

--**********************************************************************************

--* Main clock PLL

--**********************************************************************************

myAltPll_inst : myAltPll PORT MAP (

areset => reset,

inclk0 => mainClk,

c0 => clk,

locked => pllLock

);

--**********************************************************************************

--* LEDs

--**********************************************************************************

leds <= switches( 3 downto 0 );

--**********************************************************************************

--* lsasBus : inout std_logic_vector( 31 downto 0 )

--**********************************************************************************

lsasBusIn <= lsasBus;

lsasBus_tristate:

process( lsasBusEn, lsasBusOut, lsasBusIn ) is

begin

for index in 0 to 31 loop

if lsasBusEn( index ) = '1'  then

lsasBus( index ) <= lsasBusOut ( index );

else

lsasBus( index ) <= 'Z';

end if;

end loop;

end process;

system : SPI_Avalon_System 

   port map(

      clk_clk        => mainClk,

   reset_reset_n  => reset,

   spi_mosi       => lsasBusIn(15),

   spi_sclk       => lsasBusIn(13),

   spi_ss         => lsasBusIn(12),    

   spi_miso       => lsasBusOut(14),

      en_miso        => lsasBusEn(14),

state          => state,

ss_sys => lsasBusOut(5)

);

lsasBusOut(4 downto 0) <= state(4 downto 0);

lsasBusEn(5 downto 0) <= (others => '1');

lsasBusOut(8)<=lsasBusIn(13);

lsasBusEn(8)<= '1';

state_out <= state;

end behavioural;

------------------------------------------------------------------------------

FPGA-USER.vo --- FIRST COMPILATION

`timescale 1 ps/ 1 ps

module user (

          mainClk,

          slowClk,

          reset,

          mcuUartTx,

          mcuUartRx,

          mcuI2cScl,

          mcuI2cSda,

          lsasBus,

          switches,

          leds,

          state_out);

input mainClk;

input slowClk;

input reset;

input mcuUartTx;

output mcuUartRx;

input mcuI2cScl;

inout mcuI2cSda;

inout [31:0] lsasBus;

input [7:0] switches;

output [3:0] leds;

output [4:0] state_out;

------------------------------------------------------------------------------

FPGA-USER.vo ----SECOND COMPILATION

`timescale 1 ps/ 1 ps

module user (

          mainClk,

          slowClk,

          reset,

          mcuUartTx,

          mcuUartRx,

          mcuI2cScl,

          mcuI2cSda,

          lsasBus,

          switches,

          leds,

          state_out);

input mainClk;

input slowClk;

input reset;

input mcuUartTx;

output mcuUartRx;

input mcuI2cScl;

output mcuI2cSda;

output [31:0] lsasBus;

input [7:0] switches;

output [3:0] leds;

output [4:0] state_out;

[FvM]

Hi,
just a guess, you see inout port implemented as output only because tri-state output is always enabled in your code. If so, you'd see respective synthesis warnings.

[Gianfranco9635]

Hi,
The tri-state outputs are not always active. In fact my lsasBusEn is initialize to 0.

Maybe I’m wrong. How would you fix my code?

Thank you!!

[ShengN_Intel · Accepted solution]

Hi,

Check this KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000086339.html, this is known previous problem and had been concluded using the workaround clean the project before running compilation to resolve the problem. Based on previous internal team reply: There is no capacity or further step taken for this.

The problem only exists in linux version but not in window version.

Thanks,

Regards,

Sheng

[Gianfranco9635]

Hi,
I’m using quartus lite 20.1 in Windows.

if I use clean project under project tab, it works good. But if I want to clean it automatically every time that I want to compile, what I should do? Create a script and add it on project?

thanks

[ShengN_Intel]

Hi,

Yes, you can create a tcl script for example like test.tcl. Then add the command below to the tcl script:

quartus_sh --clean test

quartus_sh --flow compile test

And then source the tcl script to clean and compile

[Edited] If for quartus_sh --clean test, project name test can't be used then use with the .qpf one like test.qpf

[ShengN_Intel]

Or you may also create tcl script like below and run with quartus_sh -t:

package require ::quartus::project

package require ::quartus::flow

project_open -revision test test

project_clean

project_open -revision test test

execute_flow -compile