Input pin is held high (3.3V LVCMOS)

[Altera_Forum]

Hello,

I have a Cyclone III and a simple fan out board (my own design, just a fan out of all pins). I'm trying to learn how to use the PLL megafunction. Basically I've programmed the FPGA to what I thought uses 2 inputs and 2 outputs:

inputs:

areset

inclk0

outputs

locked

c0

The VHDL autogenerated by quartus II using the megafunction is below:

(ATTACHED).. Post was too long

I was getting 2 critical warnings about time constraints so I added a .sdc file using another wizard with TimeQuest:

# Clock constraints

create_clock -name "inclk0TC" -period 31.250ns [get_ports {inclk0}] -waveform {15.500 1.000}

# Automatically constrain PLL and other generated clocks

derive_pll_clocks -create_base_clocks

# Automatically calculate clock uncertainty to jitter and other effects.

derive_clock_uncertainty

# tsu/th constraints

set_input_delay -clock "inclk0TC" -max 30.25ns [get_ports {inclk0}] 

set_input_delay -clock "inclk0TC" -min 1.000ns [get_ports {inclk0}] 

# tco constraints

set_output_delay -clock "inclk0TC" -max 30.25ns [get_ports {c0}] 

set_output_delay -clock "inclk0TC" -min -1.000ns [get_ports {c0}] 

# tpd constraints

set_max_delay 2.000ns -from [get_ports {inclk0}] -to [get_ports {c0}]

I now get these warnings:

Warning: Parallel compilation is not licensed and has been disabled

Warning: Parallel compilation is not licensed and has been disabled

Warning: Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.

Warning: Ignored create_clock at ddr_pll.sdc(26): Option -waveform: Invalid waveform definition

Info: create_clock -name "inclk0TC" -period 31.250ns [get_ports {inclk0}] -waveform {15.500 1.000}

Info: create_clock -name "inclk0TC" -period 31.250ns [get_ports {inclk0}] -waveform {15.500 1.000}

Warning: Ignored filter at ddr_pll.sdc(37): inclk0TC could not be matched with a clock

Warning: Ignored set_input_delay at ddr_pll.sdc(37): Argument -clock is not an object ID

Info: set_input_delay -clock "inclk0TC" -max 30.25ns [get_ports {inclk0}] 

Info: set_input_delay -clock "inclk0TC" -max 30.25ns [get_ports {inclk0}] 

Warning: Ignored set_input_delay at ddr_pll.sdc(38): Argument -clock is not an object ID

Info: set_input_delay -clock "inclk0TC" -min 1.000ns [get_ports {inclk0}] 

Info: set_input_delay -clock "inclk0TC" -min 1.000ns [get_ports {inclk0}] 

Warning: Ignored set_output_delay at ddr_pll.sdc(43): Argument -clock with value [get_clocks {inclk0TC}] contains zero elements

Info: set_output_delay -clock "inclk0TC" -max 30.25ns [get_ports {c0}] 

Info: set_output_delay -clock "inclk0TC" -max 30.25ns [get_ports {c0}] 

Warning: Ignored set_output_delay at ddr_pll.sdc(44): Argument -clock with value [get_clocks {inclk0TC}] contains zero elements

Info: set_output_delay -clock "inclk0TC" -min -1.000ns [get_ports {c0}] 

Info: set_output_delay -clock "inclk0TC" -min -1.000ns [get_ports {c0}] 

Warning: PLL "altpll:altpll_component|ddr_pll_altpll:auto_gener ated|pll1" is in normal or source synchronous mode with output clock "compensate_clock" set to clk[0] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins

Warning: PLL "altpll:altpll_component|ddr_pll_altpll:auto_gener ated|pll1" output port clk[0] feeds output pin "c0~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

Warning: 2 pins must meet Altera requirements for 3.3-, 3.0-, and 2.5-V interfaces. For more information, refer to AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems.

Info: Pin areset uses I/O standard 3.3-V LVCMOS at 22

Info: Pin inclk0 uses I/O standard 3.3-V LVTTL at 91

Info: Pin areset uses I/O standard 3.3-V LVCMOS at 22

Info: Pin inclk0 uses I/O standard 3.3-V LVTTL at 91

Warning: Parallel compilation is not licensed and has been disabled

Warning: Ignored create_clock at ddr_pll.sdc(26): Option -waveform: Invalid waveform definition

Info: create_clock -name "inclk0TC" -period 31.250ns [get_ports {inclk0}] -waveform {15.500 1.000}

Info: create_clock -name "inclk0TC" -period 31.250ns [get_ports {inclk0}] -waveform {15.500 1.000}

Warning: Ignored filter at ddr_pll.sdc(37): inclk0TC could not be matched with a clock

Warning: Ignored set_input_delay at ddr_pll.sdc(37): Argument -clock is not an object ID

Info: set_input_delay -clock "inclk0TC" -max 30.25ns [get_ports {inclk0}] 

Info: set_input_delay -clock "inclk0TC" -max 30.25ns [get_ports {inclk0}] 

Warning: Ignored set_input_delay at ddr_pll.sdc(38): Argument -clock is not an object ID

Info: set_input_delay -clock "inclk0TC" -min 1.000ns [get_ports {inclk0}] 

Info: set_input_delay -clock "inclk0TC" -min 1.000ns [get_ports {inclk0}] 

Warning: Ignored set_output_delay at ddr_pll.sdc(43): Argument -clock with value [get_clocks {inclk0TC}] contains zero elements

Info: set_output_delay -clock "inclk0TC" -max 30.25ns [get_ports {c0}] 

Info: set_output_delay -clock "inclk0TC" -max 30.25ns [get_ports {c0}] 

Warning: Ignored set_output_delay at ddr_pll.sdc(44): Argument -clock with value [get_clocks {inclk0TC}] contains zero elements

Info: set_output_delay -clock "inclk0TC" -min -1.000ns [get_ports {c0}] 

Info: set_output_delay -clock "inclk0TC" -min -1.000ns [get_ports {c0}] 

Warning: Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER

I was only getting 10 warnings before so I think the last 10 here are related to my timing constraints.

My assignment editor looks like this:

c0 Location PIN_70 Yes 

inclk0 Location PIN_91 Yes 

locked Location PIN_63 Yes 

areset Location PIN_22 Yes 

inclk0 I/O Standard 3.3-V LVTTL Yes 

c0 I/O Standard 3.3-V LVCMOS Yes 

areset I/O Standard 3.3-V LVCMOS Yes 

locked I/O Standard 3.3-V LVCMOS Yes 

c0 Current Strength 8mA Yes ddr_pll

locked Current Strength 8mA Yes ddr_pll

It was my understanding that the output current strength on Cyclone III devices must be at least 8mA. I can't recall which datasheet I saw that on so sorry I can't point to the reference right now on that current strength.

So the pins I chose are for dedicated input clock pin and PLL pin for output.

The way I have my board wired right now is all pins are floating except inclk0 pin I'm scoping right now via a female header (fan out board just have all pins exposed via female headers).

I'm programming the FPGA using Active Serial so my config device (EPCS16) has a copy of the binary.

SOOOOOO. The short of the long is should I be setting something else so that the input pin (dedicated clock pin) for inclk0 signal is not being pulled high internally? I"m not really sure why I see this pin pulled to a level. When I apply the clock signal (looks more like a sinusoidal signal rather than square wave) I can scope what I see at the FPGA and it basically just looks like the same signal (sine wave) but with DC offset at 3.3V. So my clock driver is not pulling the input pin in one direction or another, it's just the AC wave superimposed on the DC line. It makes sense to me electrically but how do I rid this offset? Also note that the PLL output pin for signal c0 right now is just sitting at a high level as well (and the locked pin indicator).

I'm totally at a loss.. Been trying to monkey with this thing on and off for a good year now but I haven't had any luck getting this clock thing to work.

My current goal is basically just to pass my crappy looking clock into the FPGA, use the PLL to 'square' the waveform, and pass the square wave out so I can drive another piece of electronics with the square wave. I intend to use the FPGA for more than that! But this has been a hold up for me until I can get a decent looking clock. I require to have the clock in the FPGA anyways so I can sync the output of my other IC with the FPGA for grabbing data later down the line. The clock is the first step though!

Any help or suggestions welcome! Thanks!