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Inquire about the default state of I/O Pins

H_K1
Beginner
‎06-20-2024 02:31 AM
522 Views

Hi 
I am currently working on project involving Intel/Altera 5CSEBA4V2317N specifically focusing on FPGA I/O Bank : PL Bank 3B.

Could you please provide the information of default state of these pins ( High, Low, High impedance) when the FPGA is not programmed ?


Thankyou.

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NormanS_Intel
Moderator
‎06-23-2024 06:28 PM
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Hello H_K1,

 

Thank you for posting in the community!

 

To ensure you receive the most specialized assistance, we have a dedicated forum that addresses these specific concerns. Therefore, I will be moving this discussion to our FPGA Forum. This will allow our knowledgeable community and experts to provide you with timely and accurate solutions.

 

Best regards,

Norman S.

Intel Customer Support Engineer


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