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Sure, instantiate the HDL directly in your design. For example, see the designs in these threads ...
http://www.alteraforum.com/forum/showthread.php?t=45927 http://www.alteraforum.com/forum/showthread.php?t=43992 Cheers, Dave--- Quote Start --- Wouldn't that mess up if the Qsys design changed the HDL files used in the design? Isn't it always better to include the qip or qsys file when using qsys? --- Quote End --- That is not what the original poster asked. You can have a top-level HDL file that is not the Qsys file. You can then include an instance of the Qsys system at some level within your HDL design. Your Quartus project then needs to include either the .qsys file or the .qip file. I prefer to include the .qip file, and I use Tcl scripts to check the status of the .qsys file, eg., if its edited, the Tcl script regenerates the Qsys HDL. If you look at the scripts for the design examples linked above, you will see some other advanced uses of Tcl, eg., the DE0-nano SDRAM design does not include a .qsys file, it generates one from a Tcl script. This makes the script portable among different versions of Quartus (the .qsys file is not portable). Cheers, Dave
