Hello.
I'd like to ask a question about DDR3 example design for Intel Arria 10 GX Development Kit (DK-DEV-10AX115S-A).
I'm facing at the traffic generator test failure (traffic_gen_fail = 1) after getting the calibration success (local_cal_success = 1).
The conditions are followings:
Tool and device:
- Quartus Prime Pro 22.4
- Arria 10 GX Development Kit (DK-DEV-10AX115S-A)
- DDR3 HILO module bundled with Development Kit
- Board Test System (bts_ddr3.sof) passed with no errors
DDR3 IP
- External Memory Interfaces Intel Arria 10 FPGA IP (DDR3)
- Applied the preset for DDR3 HILO for Arria 10 GX Development Kit
- No additional modification applied to the IP configuration
- Generate Example Design
Example Design
- LED D3 Green (local_cal_success), LED D10 Red (traffic_gen_fail) are ON
- The simulation provided with the example design passes, thus it reaches both local_cal_success and traffic_gen_pass asserted.
- With Signal Tap, address and writedata matches the simulation result, on the other hand, readdata looks unmached from the first data when the traffic generator test started.
- With External Memory Interface Toolkit, the calibration report looks fine.
- If DDR3 IP configured with Efficiency Monitor Interface, it shows 89.04%, the other reports look fine to me.
Others
- I have tested with several Arria 10 GX Development Kit boards, however, they shows same symptom.
I'll appreciate if any information to solve this situation.
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