Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21174 Discussions

Intel® Cyclone® 10 GX EMIF Pins Drive Strength and Slew Rate

HamzahS
New Contributor I
‎06-06-2021 04:09 AM
348 Views

Hi,

 

We are designing a board that has EMIF and we have a few questions as follows:

  • On what bases do we set the drive strength and the slew rate of the DDR memory pins?
  • Is there a limit that does not allow all pins of the IO bank to be set with the maximum drive strength or lowest slew rate?

 

Thanks,

-Sulaiman

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.