Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20688 Discussions

Intel® Cyclone® 10 GX EMIF Pins Drive Strength and Slew Rate

HamzahS
New Contributor I
253 Views

Hi,

 

We are designing a board that has EMIF and we have a few questions as follows:

  • On what bases do we set the drive strength and the slew rate of the DDR memory pins?
  • Is there a limit that does not allow all pins of the IO bank to be set with the maximum drive strength or lowest slew rate?

 

Thanks,

-Sulaiman

0 Kudos
0 Replies
Reply