Hi,I am working with Quartus 17.1 and I have compiled a project using HLS. I am able to generate the project directory and the associated verilog files. I have used the -ghdl flag while using i++ to compile for the Arria10 FPGA platform. The vsim.wlf is generated in the <project_dir>/verification folder and I am able to open that on Modelsim as well. However, when I run the project executable, I receive the message "The simulation process encountered an error and has been terminated." This is the error generated by the transcript.log file of Modelsim. This is attached as intel_hls_simulation_error.png below. Curious, I went ahead to look at the specified line in the transcript. That is attached as break_in_module.png below. I am not able to make sense of this error. I tried to run the the given example files as well, however, I faced the same issue. The simulation got terminated that time as well. Therefore, I do not believe it is my HLS code which is breaking the simulation. I do not understand the reason for this. Please provide inputs or fixes, if any. Thank you! NOTE: I am working with Centos 6.8 and have the necessary packages installed. I used to use Centos 7.4 but had to revert to 6.8 upon finding out that arbitrary datatypes were not being supported in Centos 7.4.
Can you please provide the whole log file. Generally the issue with windows is the long path or in simulation there is not enough memory. I can tell more with the log.