Intel SFL IP Core in top-level module used to configure serial configuration device causing ID error

[EmmaT]

Hi,

I am having difficulty using the instantiated Intel FPGA Serial Flash Loader IP Core in my top level design to load newer firmware versions for the FPGA into a serial configuration device.

I have created an instance of the SFL IP core without the "Share ASMI interface in your design" option selected and am feeding a low signal into the noe_in input in my top-level design. I use the Quartus programmer to load the generated .sof file onto the FPGA. When I go to load the same configuration data in .jic format, I get the error:

Info (209060): Started Programmer operation at Wed Mar 24 13:18:37 2021
Info (209016): Configuring device index 1
Info (209017): Device 1 contains JTAG ID code 0x02B140DD
Info (209007): Configuration succeeded -- 1 device(s) configured
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Wed Mar 24 13:19:08 2021
Info (209060): Started Programmer operation at Wed Mar 24 13:19:38 2021
Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
Error (209025): Can't recognize silicon ID for device 1. A device's silicon ID is different from its JTAG ID. Verify that all cables are securely connected, select a different device, or check the power on the target system. Make sure the device pins are connected and configured correctly.
Error (209012): Operation failed
Info (209061): Ended Programmer operation at Wed Mar 24 13:19:44 2021

When programming, only the .jic file is selected to be programmed - not the Factory Default enhanced SFL image as well.  I am programming via JTAG interface using EthernetBlaster. Programming the serial configuration device with the .jic using the Factory Default enhanced SFL image works successfully.

Edit: issue resolved.

[YuanLi_S_Intel]

Hi Emma,

So you are saying that when you attached the JIC for FPGA only, you are able to program it. But it is not when you are attaching JIC with normal image and JIC with SFL IP?

Please clarify.

Thank You