Interfacing DDR or SRAM

[Altera_Forum]

Hello, 

 Iam so sorry for my newbie question but i've already read sooo many literature but iam not sure what is what.  Sooo. I need high count of BLVDS. Iam using it on my backbone as data communication interfaces so there is 96 BLVDS for data and 18 BLVDS as clock sources. The datas are transfered serialy in 16 frames each 32bits 384000 times per second.  because it is time sensitive i need to store it into temp memory (DDR2 or SRAM) and then send to another periheral.(Function as router) so i need to transfer 49152bits per 1/384000s so it is 18 874,368 Mbits/s.  Now the question. Because of needs of reading and writing into RAM's i have two options.  1: Double the data bandwidth 2: double the count of memory and switch between them (ping-pong).  I've choose the second option and using two memory with 32bits width interface.But, the maximum clock for DDR2 in cyclone IV is 200MHz (Because cyclone V does not support BLVDS). So what is maximum bandwidth for DDR2 in cyclone IV? if DDR's are 4n prefetch then bandwidth is 200 MHz x 32b x 4 = 25 600 Mbit/s. Is it right? Will the PHY in Cyclone IV support this bandwidth?Also i dont know how many % of bandwidth will consume refreshing of datas in the DDR.  If i will use SRAM (that consumes much more IO's than DDR) then at frequency 250MHz and data bus width 32b will maximum bandwidth 8000 Mbit/s so i would need 3 chips for read and 3 for read that i would switch. And i am still not sure that IO pins will be enough fast.  So what should i use?  Many thanks for advices.

[Altera_Forum]

--- Quote Start ---  Because cyclone V does not support BLVDS  --- Quote End ---   Not completely right. AN522 suggests to use Differential SSTL-2 to implement BLVDS with Cyclone V.    --- Quote Start ---  if DDR's are 4n prefetch then bandwidth is 200 MHz x 32b x 4 = 25 600 Mbit/s.  --- Quote End ---   Can't follow your calculation. DDR is double data rate, not quad data rate. In addition, you can stream out a full row continuously, but some housekeeping and setup of next transfer has to be performed. Expect e.g. 95% of burst transfer rate for large blocks. Performing concurrent read and write will further halve the bandwidth.