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Altera_Forum
Honored Contributor I
1,909 Views

Interfacing of Cyclone V GX starter kit with AFE5809EVM

I'm new to Altera devices and i am working on a project to interface AFE5809EVM with cyclone V GX starter kit using the HSMC-ADC-Bridge connector. Does anyone has any knowledge about how to do it. Please let me know.  

 

 

Thank You !! 

 

Regards 

Nimish
0 Kudos
10 Replies
Altera_Forum
Honored Contributor I
53 Views

Hi, 

 

Refer previous thread 

https://alteraforum.com/forum/showthread.php?t=44049 

Hope this could help you. 

Signal generator(SRC)->AFE5809EVM (ADC)->FPGA(Digital processing) convert Differential to signal-ended signal->serially output the data. because of the trace capacitance, you may get the same signal as an input signal.  

1. AFE5809EVM Differential serial output needs to be interfaced to FPGA using an HSMC-ADC-Bridge connector. 

2. Establish the clock synchronisation between the FPGA and AFE5809EVM. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
53 Views

Thanks for your time !! 

 

I just wanted to know can we use HSMC-ADC-Bridge to convert the Differential data coming from AFE to Single Ended to be transmitted to FPGA and can we control the triggering operations through FPGA like can it control AFE on when to start the conversion and send data and when to stop it. 

 

Regards 

Nimish
Altera_Forum
Honored Contributor I
53 Views

Hi Nimish, 

 

HSMC-ADC-Bridge? Dose HSMC-ADC-Bridge(adapter) have any IC to convert Differential to single-ended?  

Why can't, the inputs to FPGA be Differential? 

 

can we control the triggering operations through fpga like can it control afe on when to start the conversion and send data and when to stop it. 

tx_sync_in( System trig signal input) It indicates the start of signal transmission from "J11" and ADC clock can be used. You can use FPGA logic to synchronize/or control the triggering operation. 

Do check the AFE5809EVM datasheet and user guide for more information. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
53 Views

Hi Anand. 

 

HSMC-ADC-Bridge is just a basic connector and does not possess any IC and regarding the Differential input, you suggested to convert the differential ended data to single ended so that's why we are considering this. Can we use differential input. 

 

Regards, 

Nimish
Altera_Forum
Honored Contributor I
53 Views

Hi, 

 

I had asked for FPGA output side to convert to single-ended. 

Refer http://www.farnell.com/datasheets/2099782.pdf 

http://www.ti.com/lit/ds/symlink/afe5809.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
53 Views

Hi, 

 

If you're chip uses LVDS signalling, you can interface it to FPGA via the HSMC bridge. Make sure the input pins for these signals are set as LVDS in the pin planner. This way you will be able to read in the LVDS data from the chip into the FPGA. The LVDS IO at the FPGA will convert the differential signals to single-ended ones internally at the IOBUF level. Thus you will get single-ended signals from the LVDS IO inside the FPGA and you can use it for other logical purposes in the core logic.  

 

Does this answer your question?
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Hi, 

 

If you're chip uses LVDS signalling, you can interface it to FPGA via the HSMC bridge. Make sure the input pins for these signals are set as LVDS in the pin planner. This way you will be able to read in the LVDS data from the chip into the FPGA. The LVDS IO at the FPGA will convert the differential signals to single-ended ones internally at the IOBUF level. Thus you will get single-ended signals from the LVDS IO inside the FPGA and you can use it for other logical purposes in the core logic.  

 

Does this answer your question? 

--- Quote End ---  

 

 

Hi, 

 

So it means we have to connect the LVDS I/O pins of FPGA to the HSMC Connector which automatically convert the differential signals to single-ended ones?  

And do you have the required VHDL Interfacing code for FPGA with AFE. It will help for any reference. 

 

Best Regards, 

Nimish
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Hi, 

 

I had asked for FPGA output side to convert to single-ended. 

Refer http://www.farnell.com/datasheets/2099782.pdf 

http://www.ti.com/lit/ds/symlink/afe5809.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Hi, 

 

Thanks for your time. I"ll look forward to it. 

 

Best Regards, 

Nimish
Altera_Forum
Honored Contributor I
53 Views

 

--- Quote Start ---  

Hi, 

 

I had asked for FPGA output side to convert to single-ended. 

Refer http://www.farnell.com/datasheets/2099782.pdf 

http://www.ti.com/lit/ds/symlink/afe5809.pdf 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Hi, 

 

Are the pin out of the HSMC in the Cyclone V GX Starter kit Schematics right? It does not match with the schematic of the HSMC-ADC-Bridge. Can you please assure it.  

Also it would be great if you can help me in pin planning of these LVDS signals from HSMC-ADC-Bridge. 

 

Regards, 

Nimish
mreca
Beginner
53 Views

Hi Nimish,

 

Actually I am working in a project, and I have to use the Afe5809evm and the cyclone V GX.

  • I would like to know if you propertly connect both (the module and the FPGA) to pass all LVDS data?
  • Do you use the TSW1400evm Quartus firmware inside the Cyclone V GX to deserialize the LVDS signal?

I would really appreciate it if you could give me a hand because I do not find much information about that.

 

Regards,

Mateo

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