Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21600 讨论

Interfase with sub-LVDS i/o

Altera_Forum
名誉分销商 II
2,555 次查看

Hi all. 

Did any body try to connect altera LVDS i/o to sub-LVDS i/o standard device? What adaptation did you use? 

Thanks in advance
0 项奖励
2 回复数
Jens
新手
1,640 次查看

Hi,

 

I'm planning to connect a sensor via Sub-LVDS interface to an Arria 10 FPGA. Just a receiver is needed.

Has anyone had experience with it?

When looking in the device datasheet Arria 10 supports only LVDS. But the voltage levels are similar to Cyclone 5 devices

which supports both LVDS and Sub-LVDS.

(see attachments)

The Sub-LVDS interface of the sensor provides a common mode voltage of 0.9V, the differential output voltage is 150 mV.

It looks like it works with Arria 10 for data rates below 700 Mbps. But it is not clear what is the minimum VID when VCM = 0.9V?

The question is can Arria 10 used as a Sub-LVDS receiver?

Where are the differences between Cyclone 5 Sub-LVDS and Arria 10 LVDS interface (accept the data rate limitation)?

Any suggestions?

 

Jens

0 项奖励
Jens
新手
1,640 次查看

Why I can not attach 2 files in one post?

Please have a look at this second attachment here.

 

Jens

0 项奖励
回复