Is a SRAM necessary in a cycloneiii?

[Altera_Forum]

Is a SRAM necessary in a cycloneiii system? 

Can I use a sdram as a program memory instead use a sram? Or can I use two individual sdrams in the same system?

[Altera_Forum]

I guess, you are talking about a system with a NIOS II processor. It requires SRAM for effective operation.

[Altera_Forum]

If your application is very small, it could fit in on-chip memory... But even the biggest Cyclone III has about 300 kbytes of ram. 

If you need external memory you can use sram or sdram. Just pick the right controller when you design your sopc system. You can also use several chips, or combine sram and sdram, depending on your needs.

[Altera_Forum]

Wouldn't it be more precise to specify the SRAM needed to be effective ? 

a Sram could be >100nSec slow and a sdram clock with ~125MHz faster but an SRAm could also be very fast <12nSec .....  or do you mean the internal memory blocks used for cache, tightly couple memory and other high speed memory stuff ?  to answer his second question, yes of course sdram can be used for program memory but be aware that you need some other memory where your program is stored, nios must boot and copy your instructions into sdram and then execute from there.  for the last question, you can add as much memory devices as possible depending on available pins and others criteria. so no problem to add flash, sdram, nvram, and other external type of memories at the same time.

[Altera_Forum]

--- Quote Start ---  I guess, you are talking about a system with a NIOS II processor. It requires SRAM for effective operation.  --- Quote End ---     Thank you all. To FvM:Which effective operation is of SRAM? To DaiXiWen: My application is very big and the SRAM capability is too little. To MSchmitt :I want to use reset address to on-chip memory and program data in ddr.Does I can do that?

[Altera_Forum]

When you create your Nios processor in SOPC builder, select the on-chip memory for the exception vectors. I think it is in the first window of the processor properties. 

Then before compiling your application, in the IDE, go to the system library, select the ddr as program memory, and your application will be loaded in the ddr. You can also set there the memory used for static data, stack and heap.  Don't forget to connect the NIOS instruction Avalon master to the DDR controller in SOPC builder!

[Altera_Forum]

--- Quote Start ---  To FvM:Which effective operation is of SRAM?  --- Quote End ---   Programm execution from SDRAM is involving larger latency, for this reason most NIOS applications are using SRAM for code, also Altera and Terasic Dev Kits. But it must not necessarily be the best choice for your application.

[Altera_Forum]

But cache can compensate this more or less. 

 We monitor the SDRam acces to see whether the cache size is big enough or not. If on chip memory is available then unused blocks will be used for cache if possible (it is paid memory)  If you run from SRAM then your application must fit into this chip and fast sram is expensive compared to sdram.  so it realy depends on the application