Is it a synthesizable verilog coding?

Altera_Forum · ‎05-11-2015

I delete it.

Altera_Forum · ‎05-11-2015

In that particular example it *should* be fine, because it is effectively equivalent to:


wire rst_n = !(B & C);
always @ (posedge A or negedge rst_n) begin
    if(~rst_n) begin
        E <= 0;
    end else if (D) begin
        E <= F;
    end
end

A is still used as the clock, and D is used as a clock enable.

Altera_Forum · ‎05-11-2015

--- Quote Start ---

In that particular example it *should* be fine, because it is effectively equivalent to:


wire rst_n = !(B & C);
always @ (posedge A or negedge rst_n) begin
    if(~rst_n) begin
        E <= 0;
    end else if (D) begin
        E <= F;
    end
end

A is still used as the clock, and D is used as a clock enable.

--- Quote End ---

Thank you.

After post this, I try use Quartus "Technology Map Viewer", and it give me the answer.

Thank you anyway, you're very kind.