Hi forum.I'm a total noob to this business, and would appreciate if you could share your knowledge on this matter: In my project I just have one available clock, and it's a NTSC "color clock" of apx 3,5MHz. I would need to multiply it at least 8 times for my internal logic. Can I do this using the built-in PLLs of the MAX 10 (10M08SC), or do I have to resort to an external PLL circuit? (Like the OnSemi NB3N502) So far I have just tried the ALTPLL Megafunction, and noticed it wouldn't accept lower values than "5" in the input box. Is that final, or can it be tweaked somehow? I have also read through the MAX 10 PLL and CLK user guide, but I'm not sure if understood all parts of it (I'm really new to this :oops:). However, I couldn't find much mentioning of lower limits or "Fmin" and such. Any help or pointers are much appreciated.
Max 10 datasheet indicates absolute minimum frequency input to the PLL is 5MHz.Ref datasheet timing / electrical specs, page 26:
PLL Specifications Table 27. PLL Specifications for MAX 10 Devices VCCD_PLL should always be connected to VCCINT through decoupling capacitor and ferrite bead. Symbol Parameter Condition Min Typ Max Unit fIN Input clock frequency — 5 — 472.5 MHzIf you could 2X the frequency to ~7.2MHz it would be in range. So something simple like this externally: https://www.maximintegrated.com/en/app-notes/index.mvp/id/3327 would work. Or, use something like a 14.31818MHz oscillator to feed into your FPGA, and multiply up from that. And divide this frequency down by four to feed to your external logic that requires 3.58...MHz to operate. Of course this assumes you can replace the 3.58MHz signal source with another source (may not be possible, depends on your external circuitry).
If you're just experimenting on the bench, and not designing a "real product", you can try feeding the 3.58Mhz to the PLL and it may lock even though it's expecting a 5Mhz input.
I would also expect the PLL locking to 3.58 MHz reference with nominal 5 MHz input. But it's not guaranteed by spec. The lock range might be affected by PVT variation.It's also possible to implement a kind of software PLL/DLL, utilizing PLL dynamic phase shift feature.
Wow, that sounds advanced... As I mentioned before, I'm a beginner in this field.Maybe in time, I will get back to the more exotic features of the PLL, so thanks for the tip. I'll keep it in mind.