every new FPGA project with Altera/Intel FPGA was/is an adventure.
First off all it is not really possible to plan an effort for new solution, because the documentation mostly never match the Quartus IP or functions.
Very simple example with an Avalon FIFO:
Step 1: IP in Quartus is called "Avalon FIFO Memory Intel FPGA IP". Now try to find this string in altera online documentation - wasted time. IP itself contain a link to ... 😂 "On-Chip FIFO Memory Core". Is it a same - nobody knows.
Step 2: Now connect this IP with your control signals. Is it easy - of couse, can you do it after first attempt? Never! There is a "very unimportant signal" called "reset_in". If you are doing this job for a long time, than you know that this signal should have an active high logic. Otherwise is would be called "reset_in_n". Also documentation says nothing about the active level (it is not necessary - develper will play around and find a right one).
... an hour later (big design) you will mention, that your FIFO makes nothing, and "Oh Wonder!" the Signal Tap calls the reset signal "xyz_reset_reset_n". 😡
Step 3: Let use a software interface to control this IP by NIOS as it is described in the online docu. Next adventure 😠 :
the write command altera_avalon_fifo_write_fifo() would like to get two addresses: WRITE and CONTROL. But the control port is optional! After some reverse engineering of the source code, you wiil find out, that the software interface it not for the CONTROLLING of the FIFO, but only to read/update status and to contol the interrupt handling. The CONTROL register is called ALTERA_AVALON_FIFO_OTHER_INFO_REG. Can you read it clearly smwh in the documentation? ... 😋 sorry it was a rhetoric question.
Proposal: If you want to start the transmission, pls use the OLD, GOOD register access.
Such situation i had mostly with ALL IPs from Altera.
My rule of trumb for Altera FPGA projects is: estimate the "normal" effort and multiply by two! Because the crowling of the correct and not missleading information becomes a part of your job (not forget the reverse engineering)
Now question to Intel/Altera support: What is a Known Good Practice proposed by you to get the correct and not missleading information about IPs!
Now question to other FPGA developers: What is your experience with Altera/Intel Documentation?
i have a lot of customers switched from Altera to your next competitor, but the reason was not a bad hardware - FPGAs are good! - but a horrible support and documentation.
My "question" is more a feedback to your company about the quality of your documentation, but you seems to be an automatic bot, that is not able to understand it.
Such things like links to altera.com in your online Wiki; or different names between the IP catalog and the documentation; or missleading software documentation costs us - developers - time and makes stress.
AGAIN: it is an open feedback. You don't need to explain me "how to open the PDF doc"- pls just improve your support, online wiki and docs.
Thanks for your feedback and it is well received and being investigated by Intel team. We would continue to improve our quality of service including documentation and support.