Is it possible to use same LVDS tx clock on different pins at same time?

[Altera_Forum]

I am playing with EP2C5T144 chip. I have two Cat5 cables to two slave devices. For my data I am using two LVDS pairs for data and one pair for transmit clock. As it is small device I am using same LVDS transmiter for both slave devices, but I can not transmit tx_Outclock to two different pairs at the same time. If I use only one pin pair(LVDS_A[2] or LVDS_B[2] either) everything is working. How to make "copy" of TX clock? 

 Quartus output:   Error: Following DDIO Output nodes could not be placed by the Fitter Error: DDIO Node "lvds:inst2|altlvds_tx:altlvds_tx_component|lvds_lvds_tx:auto_generated|lvds_ddio_out1:outclock_ddio|output_cell_L[0]" could not be constrained to a legal location Error: DDIO Node "lvds:inst2|altlvds_tx:altlvds_tx_component|lvds_lvds_tx:auto_generated|lvds_ddio_out1:outclock_ddio|output_cell_H[0]" could not be constrained to a legal location Error: DDIO Node "lvds:inst2|altlvds_tx:altlvds_tx_component|lvds_lvds_tx:auto_generated|lvds_ddio_out1:outclock_ddio|muxa_0" could not be constrained to a legal location Error: DDIO Node "LVDS_A[2]" could not be constrained to a legal location Error: DDIO Node "LVDS_B[2]" could not be constrained to a legal location

[Altera_Forum]

This is probably a limitation of the soft LVDS Megafunction, that uses DDIO cells for both data and clock outputs for optimal performance. The DDIO cells are located inside the MegaFunction and the designer most likely didn't provide an option to duplicate them. A modfied soft LVDS logic would be needed. Basically you can build it yourself using DDIO primitives.

[Altera_Forum]

I placed "ALTCLKCTRL" megafunction "for global clock" and now errors from quartus are gone. Also detected tx clock on hardware. In simulation I can see some shift between "original" clock and "clone" clock. 

 Hope, I'll test it in full hardware set after I decode how LVDS megafunction mixed bits in my output :)

[Altera_Forum]

Yes, this way you are connecting the bitclock at the PLL directly rather than routing it through a DDIO cell. What's a suitable solution depends on your LVDS speed and other requirements.