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Is it safe to interface ALTMEMPHY from another clock domain without FIFO?

Altera_Forum
Honored Contributor II
‎05-23-2012 05:30 PM
1,156 Views

Sirs, 

 

Given one ALTPLL working off 125 MHz clock and generating 300 MHz clock for DDR3 memory controller working in half-rate (read/write clock is 150 MHz) and 125 MHz for other logic. Is it safe to access DDR3 interface from 125 MHz clock domain assuming that there is only one module accessing it (i.e. no concurrent access)? My understanding is that signals like "ready", "go", "data", "data_out" are handshake signals, thus the "client" of the controller may access it directly from a different clock domain without a need for extra FIFOs synchronizing a 125 MHz client with controller's "aux_half_rate_clk" clock. Am I right? Or you have to use DCFIFO or similar thing? 

 

Thanks a bunch!
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