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Stratix V Low Latency Phy

Altera_Forum
Honored Contributor II
‎05-23-2012 06:01 PM
1,165 Views

Request for comments. 

 

I am using the Low Latency PHY in Stratix V and have an odd Critical Warning: 

 

"Critcal Warning (178012): Coreclk source from 10G RX PCS ...+ long string" 

 

Pertinent parameters are 

Data Path Type: 10G 

FPGA fabric width: 64 

PCS-PMA width: 64 

TX_Coreclkin and RX_Coreclkin are not enabled 

RX bitslip is enabled 

 

The design is Qsys based. 

 

With the above, Quartus II Megawizard is happy. However, I get the above message when compiling. The compilation does run and complete in Quartus II. I do not want to convert the PCS_PMA width to 32 as I loose the RX bitslip capability. I realize the warning is recommending the use of the TX_Coreclk. 

 

Has anyone faced this problem before? I am concerned about ignoring this. 

 

Thanks in advance
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