I tested according to the same source code (VHDL) shown below.
The reported delay was almost the same...
but "Cyclone 10 LP" gave the following timing error @300MHz clock.
Is my setting incomplete? or Really "Cyclone 10 LP" slow?
---Timing Analyzer report @Cyclone 10 LP---
DEVICE:10CL006YU256C8G
; Slow 1200mV 85C Model Fmax Summary ;
+------------+-----------------+------------------------------------------------+---------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------------+---------------------------------------------------+
; 520.29 MHz ; 225.02 MHz ; pl|altpll_component|auto_generated|pll1|clk[0] ; limit due to minimum port rate restriction (tmin) ;
---
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+------------------------------------------------+--------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------------+--------+---------------+
; pl|altpll_component|auto_generated|pll1|clk[0] ; -1.111 ; -1.111 ;
---Timing Analyzer report @Cyclone IV E---
DEVICE:EP4CE6F17C8
; Slow 1200mV 85C Model Fmax Summary ;
+------------+-----------------+------------------------------------------------+------------------------------------------------+
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
+------------+-----------------+------------------------------------------------+------------------------------------------------+
; 520.29 MHz ; 402.09 MHz ; pl|altpll_component|auto_generated|pll1|clk[0] ; limit due to minimum period restriction (tmin) ;
---
; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
+------------------------------------------------+-------+---------------+
; Clock ; Slack ; End Point TNS ;
+------------------------------------------------+-------+---------------+
; pl|altpll_component|auto_generated|pll1|clk[0] ; 0.846 ; 0.000 ;
---source code (vhdl)---
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity test is
port( rst, cki:in std_logic;
ti:in std_logic_vector(1 to 2);
do:out std_logic_vector(0 to 0));
end;
architecture a of test is
component altddio_out
generic(width:natural;
oe_reg:string:="UNUSED");
port( datain_h, datain_l:in std_logic_vector(width-1 downto 0);
outclock:in std_logic;
oe:in std_logic:='1';
dataout:out std_logic_vector(width-1 downto 0));
end component;
component plltst -- generated by Megawizard plugin manager
port( areset, inclk0:in std_logic:='0';
c0:out std_logic; -- 300MHz
locked:out std_logic);
end component;
signal c0:std_logic;
signal x:std_logic_vector(1 to 2);
begin
pl:plltst port map(rst, cki, c0);
ddo:altddio_out generic map(1)port map(x(1 to 1), x(2 to 2), c0, open, do);
process(c0)begin
if c0'event and c0='1' then
x<=ti;
end if;
end process;
end;
---compiler and other condition---
Quartus Prime Lite Edition 18.1.0.625
no user assignment ... so
I/O standard=2.5V, current strength=8mA, slew rate=2
