1)my board has a EP3C25E144 and a configuration chip epcs16. i 've designed a RC circuit for short low level reset for my FPGA chip ,but here it is the AS configuration ,the data transfered from epcs16 to EP3C25E144 will take about 200ms ,and so the RC circuit keep low for delaying about 60ms is nothing for the design.Is it true that RC circuit don't work for FPGA?
2)and also my friend told me that for cIII the status after power on and the configuration data was transferred into EP3C25E144 is the initial status (the reset status that we want),maybe my friend is right ,because i took a try ,programmed the epcs16 with the AS way ,when power on ,there is nothing output until more than 20 seconds later (i don't know why it is so long? ).for verification what my friend told me?
3)in addition ,i use other FPGA chips and i can see their datasheets the pins description for global reset pin obviously ,but when EP3C25E144,there is nothing for
that.So,my question is :is it true that not all FPGA chips have the global reset pin?
4)some net friend recommended that using the configuration signal config_done for resetting when it goes high ,but if take it for a judge signal for resetting ,my design will always keep the initial state (because it keeps high level after configuration)? So ,is it suitable if do like that? thanks so much .
