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Is there any document describing Altera Jtag components?

Altera_Forum
Honored Contributor II
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I find the component **_jtag in the library of Quartus, but cann't find detailed information about it. 

 

The component is as below:  

 

component cyclone_jtag 

generic ( 

lpm_hint : string := "UNUSED"; 

lpm_type : string := "cyclone_jtag" ); 

port( 

clkdruser : out std_logic; 

ntrst : in std_logic := '0'; 

runidleuser : out std_logic; 

shiftuser : out std_logic; 

tck : in std_logic := '0'; 

tckutap : out std_logic; 

tdi : in std_logic := '0'; 

tdiutap : out std_logic; 

tdo : out std_logic; 

tdouser : in std_logic := '0'; 

tdoutap : in std_logic := '0'; 

tms : in std_logic := '0'; 

tmsutap : out std_logic; 

updateuser : out std_logic; 

usr1user : out std_logic 

); 

end component;
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Altera_Forum
Honored Contributor II
731 Views

The JTAG components are not well documented. 

 

Here's my notes: 

 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf 

 

You'll find that the cyclone_jtag is a device-specific implementation of some other generic JTAG component. 

 

What were you trying to implement? 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
731 Views

Hi, Dave, 

 

I am trying to use these family_jtags to connect our JTAG-supported soft modules(inside FPGAs), so we can access both vendor's JTAG component and our soft modules by software. 

 

Your notes give the information about virtual jtag, but the component "family_jtag" is the primitive. What I really want to use is the primitive. 

 

Is there any detailed information about this component's pinout?
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Altera_Forum
Honored Contributor II
731 Views

 

--- Quote Start ---  

 

I am trying to use these family_jtags to connect our JTAG-supported soft modules(inside FPGAs), so we can access both vendor's JTAG component and our soft modules by software. 

 

Your notes give the information about virtual jtag, but the component "family_jtag" is the primitive. What I really want to use is the primitive. 

 

Is there any detailed information about this component's pinout? 

--- Quote End ---  

 

 

The *only* supported JTAG component is the SLD_Virtual_JTAG component. Altera's JTAG-to-Avalon components are internally constructed from a component that is essentially identical to this part too, eg., see these notes: 

 

http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf 

 

I'm still not quite clear on your requirements: 

 

1) If you have a JTAG-like component that you want to access, you need to connect it via the SLD_Virtual_JTAG component. 

 

2) If you have a component with registers, then you can access it via a JTAG-to-Avalon-MM bridge, just provide your component with an Avalon-MM slave interface. 

 

Can you please clarify. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
731 Views

My application is the first one. 

 

Did you mean users can not use "cyclone_jtag" component in the "..\quartus\libraries\vhdl\cyclone_components.vhd"? 

 

What's this "cyclone_jtag" component for? 

 

Regards, 

Ryan
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Altera_Forum
Honored Contributor II
731 Views

 

--- Quote Start ---  

My application is the first one. 

 

--- Quote End ---  

 

Then Altera will only support you if you use the SLD_Virtual_JTAG component. 

 

 

 

--- Quote Start ---  

 

Did you mean users can not use "cyclone_jtag" component in the "..\quartus\libraries\vhdl\cyclone_components.vhd"? 

 

What's this "cyclone_jtag" component for? 

 

--- Quote End ---  

 

It might be used when creating a simulation model. 

 

You might also find that if you use a MegaWizard to instantiate a JTAG component that this component is internally used. However, direct instantiation of the SLD_Virtual_JTAG should give you identical (or at least very similar) control. 

 

Keep in mind that any VHDL you can read in the atoms files or the low-level device files *is not real*, i.e., you will never get to see what Altera synthesis files look like. That is all part of their secret-sauce. 

 

If you are trying to create a vendor-neutral interface to your JTAG components, then you need to go through the SLD_Vitual_JTAG components for Altera, and the BSCAN components for Xilinx, and I forget what the JTAG components are called for Lattice. Bottom line is you have to use a vendor specific component to access your vendor neutral code. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
731 Views

I see. 

 

Thanks for your advice. 

 

Regards, 

 

Ryan
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Altera_Forum
Honored Contributor II
731 Views

 

--- Quote Start ---  

 

Thanks for your advice. 

 

--- Quote End ---  

 

No problem. Hopefully it saved you some time. 

 

If you have a specific use-case that you do not want to discuss here, eg., a code example, just send me an email directly (to my forum name). 

 

Cheers, 

Dave
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