Is there any way to connect a signal to a PLL in a Max 10 without using a dedicated clock input?

[DNewm1]

Customer has protos built already but did not route clock signals to dedicated clock inputs, and they need to use the PLLs. Is there any way at all to get to the PLLs from regular I/O? Or from the fabric, etc? Are the clock inputs the only ones that will connect to PLLs in a Max 10?

[EngWei_O_Intel]

Hi Danny

In general, the reference input clock signal to the PLL must be driven by the dedicated clock input pin located adjacent to the PLL, or from the clock output signal from the adjacent PLL. Input and output delays are only fully compensated for when the dedicated clock input pins associated with that specific PLL are used as the clock source.

If the clock source for the PLL is not a dedicated clock pin for that specific PLL, jitter will increased, timing margin suffers, and the design may require an additional global or regional clock.

Thanks.

Eng Wei

[DNewm1]

Thanks Eng Wei.

A follow up and more specific question: is there a legal way to connect a signal to a PLL in a Max 10 without using a dedicated clock pin. I forgot to mention that the build fails in the fitter if any input signal from a pin other than a clock pin is connected to the PLL in a max 10 device.

[EngWei_O_Intel]

Hi Danny

If it is still in the design phase, we encourage user to follow the guideline to properly route the clock pin to avoid any impact to the functionality and performance..

In parallel, I got the response from internal team that it requires a dev-spec change approval to release the workaround (if the workaround is available for Max 10). And in order to initiate a dev-spec change, we will need a business impact justification.

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi Danny

Any update for this issue?

Thanks.

Eng Wei

[DNewm1]

Hi Eng Wei

They were able to do a quickturn respin and reassign the signal to a clock pin.  Unfortunately they also happened to choose a less-than-ideal  clock pin (i.e. one that does not allow a direct route to the single pll in this device so hopefully the design can tolerate the jitter performance).  

Thanks for you help
Danny

[EngWei_O_Intel]

Hi Danny

I will go ahead to close the ticket if there is no further issue for this topic. Let us know if you have further concern.

Thanks.

Eng Wei