In Cyclone V TRM(cv_5v4, 2020.02.28), it shows that MMC V4.41 8-bit data bus is currently supported. DDR timing is supported for eMMC too.
According to the MMC 4.41 specification， with 52MHz clock speed，eMMC can get maximum data rate to 52MB/s in single data rate mode and 104MB/s in dual data rate mode.
But in In Cyclone V TRM, the table shows that the maximum data rate is 25MB/s.
That’s quite confusing.
So does current Cyclone V support eMMC V4.41 8-bit dual data rate mode?
What’s the max data rate the cyclone V supported with 8-bit data bus?
There’s additional information about this question.
In Cyclone V TRM cv_5v4 (2014.12.15), eMMC 8-bit data bus /DDR mode was not suppported at that time. But the max data rate was 25MB/s by then. I think the max data rate should be improved while cyclone V supports eMMC 8-bit data bus and DDR mode, is that right?
Answering your questions:
Unfortunately, dual data rate is not supported, and the max supported speed is as stated in our Cyclone V TRM which is 25Mbps for 8-bit data.
For Cyclone V SoC, eMMC version 4.41 does not support DDR.