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Hi everyone,
I have a DDC logic and also runs in modelsim. Now, I want to plug into SGDMA to run. My DDC comes with multi clocks, inputs and also multi outputs. My question is that possible to run in SGDMA? My understanding is that SGDMA has only 1 input and 1 output. How can I make this into multi inputs/outputs? Anyone has done this before or could you give me some pointers? Best regards, SeanLink Copied
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what is your data flow and how do you want to connect everything together? You have some components such as mux/demux that can help.
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Thanks. Do you have template mux/demux so I can try out?
Sean- Mark as New
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They briefly talk about it in chapter 3 of the sopc user manual (http://www.altera.com/literature/ug/ug_sopc_builder.pdf). IIRC they are available in the "adapters and bridges" section in SOPC builder.
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Thanks Daixiwen,
It didn't talk much about multiplexer channel. I also read about Avalon Streaming Channel Multiplexer and Demultiplexer Cores document, but I'm really need to find a simple example mux/demux connects to SGDMA. ~Sean- Mark as New
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I think the udp offload example (http://www.alterawiki.com/wiki/nios_ii_udp_offload_example) has muxes and demuxes connected to SGDMAs, But without more details about your dataflow, it is difficult to give more advice.
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The Qsys tutorial also comes with muxes and de-muxes that are controlled by accessing a slave port. They only do 2:1 and 1:2 so if you have more channels you would have to built them up of a bunch of smaller muxes/demux (or just hack the HDL and .tcl code to support more channels).
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Thanks Daixiwen and BadOmen,
I just tried to mess around mux/demux in SOPC to connect SGDMA. Is this correct settings? I will discuss with my Researcher Manager to provide you data flow by PM interfaces. For now, I just want to see if I can learn anything from mux/demux with SGDMA. That why I just need a very simple sample with SGDMA and mux/demux. Thanks, Sean- Mark as New
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Those connections should work. However I think the SGDMA doesn't support channels, so as a result all your packets from the SGDMA will probably end up in the same stream after the demux.
IIRC the modular SGDMA doesn't support channels either, so you may have to replace the channel adapter by a component of your own that assigns a channel number to each packet.- Mark as New
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Thank you very much Daixiwen,
Yeah, I try to run Nios IDE, but I see that the result the same streaming. To BadOmen, do you have a hack in verilog file to support more than 2 channels. Best regards, Sean- Mark as New
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Without more details about what you want to do, it's difficult to tell you if this is right or not
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Thanks Daixiwen,
Ok. Here is I'm trying to do. I try to use mux/demux in between sgdma 1:3 and 3:1 to see the result from output. sgdma (mm_to_st) -> channel_adpater_A -> demultiplexer -> A (my_module) -> multiplexer ->channel_adapter_B -> sgdma (st_to_mm) When I run Nios IDE, I could see the result just 1 input (first one) and 1 output. If I assign to the second input, I get 0 result coming out. Do I need to modify demux module to make it works. Sean- Mark as New
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I think you'll have to right your own channel adapter to assign different channels numbers to your packets. On what criteria do you want to assign those packets to a specific channel?

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