Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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JESD204B RX is not locked to data


When I use Arria 10 JESD204B core to receive the data from four channels of AD6688, I find that rx_is_lockedtodata of two channels is always 0. The reference clock of transceiver remain deasserted until after Arria 10 device power up process is complete and Arria 10 device program the HMC7044 to generate this clock . On this conditon , I use user recalibration to calibrate PMA according to Arria 10 Transceiver PHY User Guide, but the rx_is_lockedtodata is still 0. But when I program the JIC and ELF file, then power up the device, the reference clock of transceiver is ready , then I program the SOF file, rx_is_lockedtodata of four channels is 1. So I think the PreSICE auto calibration can make this sucess, why user calibration is not sucessful ?

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2 Replies

​Arria 10 user guide clearly states that transceiver reference clock must be stable and free running at start of FPGA calibration. If this is not the case, the power up calibration could calibrate some of the CDR settings to values that cannot be cleared with user calibration. Hence, that's the reason you are facing the issue. Please make the transceiver reference clocks available at start of FPGA calibration to avoid the CDR cannot lock issue.




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New Contributor I

Hi Nathan, @NathanR_Intel​ 

Your answer helps. Recently I am really struggling with this Calibration thing. From your words, can I say that if FPGA is not successfully calibrated / re-calibrated, XCVRs can still run, but may with lower performance than it should be?


If you are convenient, would you like to take a look a t this thread , some further description on my questions about A10 GX device calibration.


Thanks, and happy weekend.



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