What will happen without RREFB reference resistor in the GXB?

[Altera_Forum]

Hi everyone! 

I use the Stratix II GX device to design High-Speed system,but I forgot to use the RREFB reference resistor ports .Who can tell me what will happen without the RREFB reference resistor?

[Altera_Forum]

Hello, 

 to tell you the truth, I would be surprized if normal GXB transceiver operation is possible anyway. RRef is used in GXB calibration block for termination resistor calibration. As an optimistic assumption, the calibration could fall back to meaningful default settings, possibly allowing GXB transceiver operation. Viewn pessimisticly, GXB could be completely halted due to bad calibration status. If your Stratix II devices are not yet assembled to PCB, I would consider to glue thin wires to RREF pads and connect them.   Regards,  Frank

[Altera_Forum]

Firstly, thanks a lot for FvM's help. 

Here I have anothers question. The refclk of GXB is fed by the output of the EPLL5 with the I/O standard LVDS (device EP2s30),that is the output of the device is fed to its input. And the clock becomes deformed after the LVDS receiver,just like the output of the sinusoid clock through the waveform shaping circuit, and the duty cycle of the clock increases with the frequency.When the frequency of the refclk is more than 20MHz, the output of the LVDS reveiver is just a high level.Do you think this phenomenon is correlated with the absence of rref resistance, or for other reasons? By the way, the clock is ok before the LVDS receiver that I had measured.

[Altera_Forum]

Hello, 

 the GXB refclk input is different from regular Stratix LVDS receivers, I think. According to the manual, it's AC coupled and isn't intended for operation below the minimum PLL input frequency of 50 MHz. I assume that you selected LVDS as I/O standard for the refclk input?  A wrong termination could be normally seen from the input level at the differential pins, with missing termination, the input signal would be to high but still almost symmetrical and the receiver probably operational at lower (< 100 MHz) frequency, perhaps with irregular timing.  But it could be, that the RREFB derived reference current has other uses inside the GXB block, may be also for the differential clock receivers.  Regards,  Frank

[xytech]

Hi Frank,​ 

Your answer helps. Recently I am really struggling with this Calibration thing. From your words, "recalibration is required to fine tune the internal parameters of the TX PLL, RX PMA and TX PMA to ensure that they are optimal at your new data rates. This is also to ensure that XCVR blocks will operate as expected at the new data rates", can I say that if FPGA is not successfully calibrated / re-calibrated, XCVRs can still run, but may with lower performance than it should be?

If you are convenient, would you like to take a look a t this thread , some further description on my questions about A10 GX device calibration.

https://forums.intel.com/s/question/0D50P00004Gf0dgSAB/what-would-happen-if-transceiver-calibration-fails

Thanks, and happy weekend.

[Altera_Forum]

Thans again, Frank! 

 regards,  jingyilou.

[Altera_Forum]

Altera documents state that the board layout for rrefb resistor must be very clean. Any noise introduced from the board layout can affect transceiver performance. As suggested earlier, gluing resistor through thin wires to the board pin can be an option, but it might affect transceiver performance. 

 As for the reference clock, transceiver refclk usually has strict input clock jitter requirements. Usually, output clocks from the FPGAs are not as clean as required by the high speed transceivers. One option is to bring those clocks out of the FPGA and clean them through some external clock buffer, before feeding it to high speed transceiver clock pin. AC coupling is required for Altera Transceiver clocks, except for the PCIe clock.

[Altera_Forum]

Just in case anyone is wondering what would/could happen if these resistors are missing on designs using the Arria II GX device (in my particular case it was an EP2AGX45): 

 The reference input clock will most likely not work (probably because of wrong OCT calibration due to the missing reference resistor).  I've just experienced this issue since we forgot to connect these pins according to the pin connection guidelines in our design. After somehow squeezing in a 2 kOhm resistor between ground and the FPGA ball via tiny wires (luckily this was an outside ball, so somewhat accessible) everything just started to work.  I just wanted to share this information in case someone else runs across this same issue. Unfortunately there's not enough emphasis on the importance of this particular guideline (at least it doesn't provide information on the significance).  Regards, Steffen

[xytech]

Hi Steffen, 

Your answer helps. Recently I am really struggling with this Calibration thing. From your words, "recalibration is required to fine tune the internal parameters of the TX PLL, RX PMA and TX PMA to ensure that they are optimal at your new data rates. This is also to ensure that XCVR blocks will operate as expected at the new data rates", can I say that if FPGA is not successfully calibrated / re-calibrated, XCVRs can still run, but may with lower performance than it should be?

If you are convenient, would you like to take a look a t this thread , some further description on my questions about A10 GX device calibration.

https://forums.intel.com/s/question/0D50P00004Gf0dgSAB/what-would-happen-if-transceiver-calibration-fails

Thanks, and happy weekend.