We are using Agilex F-tile and are testing it using JESD204C IP on the FPGA.
There were various issues with the JESD 204C TX, but it was confirmed that it is currently operating normally.
However, in the case of JESD RX, the problem is still being debugged.
Our current problems are as follows:
1. The CDR is normally displayed as “Locking”.
2. SH Lock is also displayed as “Locking” normally.
3. emb_lock is also displayed as “Locking” normally.
However, the CRC Error says "error" occurs once every 32 symbols.
JESD204C lock status
JESD204C lock status1
JESD204C lock status2
Of course, the 128 bits received are also not output as desired.
In the case of the other side (JESD TX), it is M company's RFIC, and the current RX is 2LANE/16G (245
.76Msps) is being used.
Currently, we are using the PRBS checker, but we cannot guarantee that the function is normal. (It is doubtful whether the data on the Tranceiver side is normal.)
I am curious if there is a way to debug CRC errors if the PRBS function cannot be used.
Also, I wonder if only the CRC problem may occur if there is a problem with the PHY characteristics (electrical characteristics) of the signal. (The lock-related bits are normal, but only the payload can be a problem...)
First of all, thank you for your reply.
Link Copied
First of all, thank you for your reply.
Q1) May I get the JESD204C configuration settings that you are using? a screenshot would be helpful.
Sure!!!
Now Now tested setting parameter of JESD204C-classb1 RX
JESD204C-classb1 TX test complete.
Q2) May I know which Quartus version, operating system and OPN that you are using for your design?
Course.
Q3) May I know is your design derive from example design or reference design? Are you using Intel devkit or custom board?
Custom design referring to JESD204C example.
Board is Custom.
FPGA<--> RFIC(MAXLINEAR)
*. 4TX(491.52Msps/4LANE/16220.26@LANE):Test Complete
*. 2RX(245.76Msps/2LANE/16220.26@LANE): This Problem
*.2FeedBack(Rx)(491.52Msps/2LANE/16220.26@LANE): Same Problem
Q4)Could you share with us your design?
Need Full Project share???
This full project is many project license. (25G ethernet, ecpri, ORAN, JESD..) and HPS sub-system.
Have license issue? We can provide.
More information need???
Our team has a question.
After doing some checking and testing, we have some questions about the issue.
FPGA JESD RX(LSB First) <-- RFIC JESD TX(MSB First)
1. Is it correct that intel JESD204C RX Phy only supports LSB First?
MSB/LSB appears to be selectable in the data sheet/Register MAP, but cannot be controlled. The F-tile PMA datasheet says that the setting is Hardcoded. What is the truth?
2. In this case, SH_Lock can be a LOCK, but emb_lock may or may not be a lock, so we don't know why emb_lock is always a lock. I'd like to ask Intel's JESD204C expert.
3. We are working to resolve the issue (LSB/MSB difference). In the case of RFIC, it is not easy to solve the problem due to control issues. (MSB First --> LSB First)
Is it possible to change LSB first to MSB first in FPGA?
If you give us an answer, we will respond after a quick test.~~
Since I don't have time, I will share other test results with you.
In the above IP (JESD204C) settings, we changed and tested many things.
We also checked many CSR Registers, and changed and tested many of them. (Actually, there were not many things that could be set.)
The FPGA part of our board is as follows:(JESD204C RX)
RFIC side(JESD204C TX)
When operating an FPGA with the corresponding IP applied, JESD RX Capture is as follows.
The timing of each LOCK that occurs at this time is as follows. (491.52M cpature base)
The order of occurrence is correct, but I don't know if the exact timing is correct (not in the document). Is that correct?(CRC_error is occurring.)
Status Register (0x60)
CDR LOCK/crc_error occurs
It was deleted, but only CDR_unlock was deleted.
The incoming data is as follows.
If normal, the signal should be All Zero.
In case of RFIC, in case of RF_RX OFF, all zero is transmitted when JESD link is alive.
csr_reinit timing(JESD RX only)
The LOCK sequence occurs the same as at the initial link_up (exact timing cannot be confirmed).: Right???
LANE Status:
Why LANE 0/1??? Isn't it LANE12 or 13?
CDR Lock Status:
CDR/SH/EMB LOCK
Polarity Inversion
IP Parameter Setting = 0x00000000, But set status = 0x00000003
Are all of these LSB <<-- MSB problems?
RFIC Company talks about RBD optimization.
Intel says that RBD optimization is automatic for the IP.
Do I need to manually optimize again?
There's a lot of content, it's hard work, but please respond.
Hi Aaronkwak,
Good day.
Apologize for the delay, please understand that I am trying my best to clarify and find answer with our internal team on this.
Below are the answer to your questions:
1. Is it correct that intel JESD204C RX Phy only supports LSB First?
Based on internal discussion, you may change this by using bit reversal operation that can be done in the user logic.
You may refer to below excel file for the Agilex registermap.
Based on our generated design example, you may change this in the rtl code located in the top file.
2. In this case, SH_Lock can be a LOCK, but emb_lock may or may not be a lock, so we don't know why emb_lock is always a lock. I'd like to ask Intel's JESD204C expert.
It is normal, for this the emb_lock must be in lock condition. Based on the JESD204C standard specs, If 4 consecutive valid sequences are detected, extended multiblock alignment is asserted (EMB_LOCK == 1).
3. We are working to resolve the issue (LSB/MSB difference). In the case of RFIC, it is not easy to solve the problem due to control issues. (MSB First --> LSB First)
Is it possible to change LSB first to MSB first in FPGA?
You may refer to my answer in Q1.
4. Intel says that RBD optimization is automatic for the IP.
Do I need to manually optimize again?
For RBD, you may need to manually set the RBD value. Different ADC/DAC vendors have different variations.
RBD count reflects on which LEMC count the latest arrival lane is. RBD offset is a user-defined value to indicate on which LEMC count the RBD is released. All lanes are aligned when RBD is released. You may need to perform calculation in order to set the RBD offset.
You may refer to below link on how to perform RBD tuning:
F-Tile JESD204C Intel® FPGA IP User Guide - 5.7. Deterministic Latency / RBD Tuning Mechanism
Q1. Could you share the detail of the RFIC?a part number or datasheet?
We would like to know more on RFIC detail to understand more on this device on how it runs, how the LSB and MSB mapping, and also on the compatibility with JESD Ip.
There are a number of factors that can cause CRC error(exp: signal integrity issue and etc)
Q2. Can you perform a loopback design on the RFIC?this is to check and isolate if the source is functioning normally.
Q3. Is the JESD configuration for the RFIC match the settings of FPGA? (example: sync header configuration(SH_config))
Best regards,
ZH_Intel
Thanks for your answer.
The reply was late because we were on New Year's holiday.
Thank you for your understanding.
Q1. Could you share the detail of the RFIC?a part number or datasheet?
There are a number of factors that can cause CRC error(exp: signal integrity issue and etc)
We would like to know more on RFIC detail to understand more on this device on how it runs, how the LSB and MSB mapping, and also on the compatibility with JESD Ip.
I know that Intel already has a group that has tested using the IC. (You can find the information in the media.)
We received an answer from the chip manufacturer saying MSB first, so we modified the information and tested it.
How to change this was not possible in IP Setting (Use GUI), and after IP Generation, .BIT_REV (1) of "jesd204c_f_rx.v" of the corresponding IP directory's synth was modified.
After this, compilation was completed, but it is unknown whether the details were applied properly. Even if you check the register map, it is the same as before: 0x[0]=0.
How should I check the results?
Also, the setting change is not 66bit reverse, but 64bit reverse. Is it possible to change 66bit reverse?
And, what I'm most curious about is whether CDR_LOCK, SH_LOCK, and EMB_LOCK can be used when 66b LSB1st<--> 66b MSB1st.
The LOCK result is ultimately the result of SH_Bit x32 = Pilot Signal, so I would like to inquire whether normal LOCK can be achieved even during LSB/MSB Reverse.
Q2. Can you perform a loopback design on the RFIC?this is to check and isolate if the source is functioning normally.
Currently, it is not easy due to the H/W structure.
As shown in the picture above, TX=4LANE, RX=2LANE.
But, I'm trying.
I am trying to change the design to 2LANE by 2LANE, but RFIC does not support PHY Loopback.
Q3. Is the JESD configuration for the RFIC match the settings of FPGA? (example: sync header configuration(SH_config))
There is no separate function for SH_Config.
The format of the SH (Pilot signal) of the corresponding IC is as follows.
Is there anything I need to change? It was confirmed that the format is identical to the JEDEC format. Are there any other materials?
===============================================================================
As a result, when changing Q1 (64b LSB --> 64b MSB) and testing, the CRC error is cleared, but new "lane_deskew_err" and "eb_full_err" occur.
We are currently STOP here.
Is there any additional confirmation?
Please understand that it is difficult to provide the MxL1600 datasheet as it is an NDA document.
Additionally, JESD TX, which has the same H/W design, is currently operating normally.
