JTAG/IO Clamping and Hot-swapping

[Altera_Forum]

I am putting Cyclone IV GX on a new board that will be configured using PS. Since all the VCCIOs are 3.3V, I am planning on clamping the the JTAG and PS config signals using a pair of schottkys between ground and 3.3V. 

If I am not mistaken, the pins that are protected by the shcottkys will lose their hot-swapping capability since if they are powered up before the 3.3V is on, the top diode will have to handle the current generated by 100% voltage swing. I do have a current limiting resistor on those pins, but if I make its value too large to handle the full 3.3V drop, it will lower the max freq through the pins. Are these valid concerns? Any clever ideas out there to deal with this? Thank you

[Altera_Forum]

--- Quote Start ---  Any clever ideas out there to deal with this?  --- Quote End ---  My personal preference is to protect JTAG and external I/O using Fairchild TinyLogic or TI LittleLogic parts.  http://www.fairchildsemi.com/products/logic/tinylogic/  You can power them from 3.0V, so you do not need the clamp diodes, and their inputs are tolerant to 7V when power is off, eg.,  http://www.fairchildsemi.com/ds/nc/nc7wz16.pdf  (http://www.fairchildsemi.com/products/logic/tinylogic/) If you are designing your hot-swap system to correctly sequence power supplies, then these buffers can be part of that sequencing.   If you are plugging into a powered backplane, then you can use hot-swap buffers with a 1V bias voltage on their output. See the following schematic for examples:  http://www.ovro.caltech.edu/~dwh/carma_board/ (http://www.ovro.caltech.edu/%7edwh/carma_board/) http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf (http://www.ovro.caltech.edu/%7edwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf)  Cheers, Dave

[Altera_Forum]

Unfortunately, the other side of the backplane is already done and provides all the needed voltages (but no 1V or 3.0V). There is no space on the new board to add LDOs for that. 

Probably I can use the tinylogic and add current limiting resistors on their output (they drive out up to 24mA). I can put the chip within 1" of the FPGA, so there may not be any issues with over/undeshoot. With this, I will not need clamping diodes. Does that make sense?

[Altera_Forum]

--- Quote Start ---  Unfortunately, the other side of the backplane is already done and provides all the needed voltages (but no 1V or 3.0V). There is no space on the new board to add LDOs for that.   --- Quote End ---  You do not need the 1V, the buffers provide it. As for the 3.0V, I was talking about the JTAG VCCIO supply. You'd use the same supply to power the buffers.    --- Quote Start ---   Probably I can use the tinylogic and add current limiting resistors on their output (they drive out up to 24mA). I can put the chip within 1" of the FPGA, so there may not be any issues with over/undeshoot. With this, I will not need clamping diodes. Does that make sense?  --- Quote End ---  The resistor on the output would be a source termination resistor, rather than a current limiting resistor. With that source termination correctly sized, there will be no overshoot. I'd recommend that approach.  Cheers, Dave

[Altera_Forum]

You are correct, those resistors are for source termination. I misspoke. I will go with your suggestion then. 

 Thank you for your help.

[Altera_Forum]

--- Quote Start ---  You are correct, those resistors are for source termination.   --- Quote End ---   Note that if you happen to have to JTAG loads, eg., TCK going to two devices, then use a dual-source termination. See examples in the design I referenced.    --- Quote Start ---   Thank you for your help.  --- Quote End ---   You're welcome.  Cheers, Dave