We instantiated a JTAG USER1 register in a Max II device by using this built-in component (VHDL):
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdouser : in std_logic;
tdo : out std_logic;
tmsutap : out std_logic;
tckutap : out std_logic;
tdiutap : out std_logic;
shiftuser : out std_logic;
clkdruser : out std_logic;
updateuser : out std_logic;
runidleuser : out std_logic;
usr1user : out std_logic);
We just needed a couple more lines of VHDL code to instantiate our USER1 register.
We are converting it to a Max 10 device, but this component does not exist. How do we do this (simply) with a Max 10 device?
The problem is that I'm using a very small CPLD devices, and this 'virtual jtag' function adds a lot of unnecessary logic that eats up space I need in the device. I'm trying to do something really simple in a very simple device. I'm just trying to add a USR register. Nothing else.
The 'component maxii_jtag' gave me exactly what I wanted, even signals the 'virtual jtag' function doesn't give, such as a clock for shifting the user register (clkdruser). I could create this from the 'virtual jtag' outputs, but that is even more logic I'd have to add.
Using the 'virtual jtag' function makes the code more complicated than it needs to be and adds a bunch of extra logic I don't need or want.
Almost every CPLD/FPGA has a function like the "component maxii_jtag". All of these exist:
Only component max10_jtag seems to be missing--the very one I want!