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Hi,
I am trying to program the CPLD with JAM Player through microcontroller. The MCU is interfaced to the CPLD through GPIO pins. I am able to prgram but unable to verify. The device failure error occurs when the verification starts. check CRC...NOTE " CREATOR" = " QUARTUS II JAM COMPOSER 13.1" NOTE " DATE" = " 2015/09/23" NOTE " DEVICE" = " 5M160Z" NOTE " FILE" = " TE70_4_SR.pof" NOTE " TARGET" = " 1" NOTE " IDCODE" = " 020A50DD" NOTE " USERCODE" = " 00175C1A" NOTE " CHECKSUM" = " 00176082" NOTE " SAVE_DATA" = " DEVICE_DATA" NOTE " SAVE_DATA_VARIABLES" = " V0, A12, A13, A25, A43, A92, A94, A95, A99, A100, A105, A109, A111" NOTE " STAPL_VERSION" = " JESD71" NOTE " JAM_VERSION" = " 2.0" NOTE " ALG_VERSION" = " 63" set device into idle state ... ok - device in idle state start JTAG ... activate JTAG-START state ... ok / activated waiting for JTAG-START state ... ok / JTAG-START state achieved. ok - JTAG started Device# Silicon ID is ALTERA10() erasing MAXII device(s)... erasing MAXII UFM block... erasing MAXII CFM block... programming CFM block... programming UFM block... verifying CFM block... Device verify failure Exit code = 11... Device verify failure Elapsed time = 0:5:31 I hav no idea why this device failure is happening. I also have the screen shot of the logic analyzer probing to the JTAG signals between MCU and CPLD is attached in the thread below. In the logic analyzer, it can be noticed that after the verification starts, after several DRSCANs and IRSCANs, at a particular instance, the CPLD output TDO goes high and remains in that level. At this point, the device verify failure occurs. Can anyone help me understand the problem here? How can this be solved? Thanks and Regards, sramy25Link Copied
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