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Norick
Beginner
1,502 Views

Jitter performance due to non-dedicated routing?!

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Hello

I am using:

  • Quartus 18.0
  • Max10

 

Now I get following warning message:

Warning (15064): PLL "... output port clk[0] feeds output pin "ADC_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

 

The design uses a PLL which goes to internal logic as well as to an FPGA output pin. In my opinion this is the reason why I get such warning.

 

Now the question is how can I solve it. How can I tell Quartus to use a "dedicated" routing to the output pin?!

 

Thanks

 

 

 

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1 Solution
a_x_h_75
New Contributor III
334 Views

I'm only assuming the "two issues" are true for your design. Without knowing more of your device/pinout I can't comment.

 

Regardless of that, I'd change it to use a single PLL using two clock outputs, ensuring you use the appropriate FPGA pin, associated with the right PLL, for ADC_CLK.

 

Cheers,

Alex

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3 Replies
a_x_h_75
New Contributor III
334 Views

I assume the your chosen pin for the ADC_CLK signal is the correct PLL_CLKOUT pin for the PLL in question...

 

Assuming so, I suspect the clk[0] port on the PLL feeds other logic, as well the the FPGA pin. If this is the case you'll get this warning. In order for the dedicated routing to be used the PLL output must only feed the FPGA pin.

 

Assuming you have one, use another PLL output configured with the same settings as the ADC clock, to feed your internal logic.

 

Cheers,

Alex

Norick
Beginner
334 Views

According to your answer, I think there are two issues to this PLL:

 

  1. The PLL_CLKOUT goes to the ADC_CLK Pin as well as to other logic
  2. ADC_CLK Pin is NOT the dedicated PLL output pin

 

 

Question:

  • Is it better to use a PLL with two outputs with
    • c0: ADC_CLK
    • c1: internal logic
  • Or two use two independend PLL's?

 

best regards

a_x_h_75
New Contributor III
335 Views

I'm only assuming the "two issues" are true for your design. Without knowing more of your device/pinout I can't comment.

 

Regardless of that, I'd change it to use a single PLL using two clock outputs, ensuring you use the appropriate FPGA pin, associated with the right PLL, for ADC_CLK.

 

Cheers,

Alex

View solution in original post

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