Jtag Working Wrong!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

[Altera_Forum]

Hi everybody! 

Recently,I'm debug a board about Ep2c8 which build by myself，after I welding end all devices，  I made a sample test program and download it with QuartusII8.0. Then Quartus tell me download success! But I find that fpga does't work as my test program!My test program just make fpga's some pins output as low! As a result ,all pins output as a high！  So ,Someone who know about it ,please tell me why!! Thank you very much!  Shenhuan 2009-11-22:confused:

[Altera_Forum]

Or who can tell me something may cause this ！ 

The signalTapII does't work too!

[Altera_Forum]

What do you mean by "signalTapII does't work"? What's the status of the CONF_DONE pin?

[Altera_Forum]

SignalTap can build and download ,but when i run it ,it show me that jtag communication error!

[Altera_Forum]

Did you setup the JTAG hardware correctly in Signaltap? Does it find your FPGA?

[Altera_Forum]

Yes!QuartusII show me download success!

[Altera_Forum]

I meant the JTAG hardware configuration in Signaltap. 

What are the levels of the nCONFIG and CONF_DONE pins after configuration?

[Altera_Forum]

nCONFIG is high and CONF_DONE is low 

!

[Altera_Forum]

CONF_DONE should be high after the FPGA has been programmed. Do you have an external pull-up on the pin?

[Altera_Forum]

Yes! Is there something others may cause this?

[Altera_Forum]

The only cause I can see is that an error occured during the FPGA configuration, but it's strange that Quartus doesn't detect it. 

There could also be a problem with one of the power supplies or a bad decoupling but I'm not sure it would prevent the COND_DONE pin from going high. Do you have another design that you can test?

[Altera_Forum]

Thanks for your advice! 

My board work now,there are something about nCS pin,because the problem of welding,nCS pin hasnot been pull down to ground!