Jtag uart causes "Verify failed" error

[Altera_Forum]

When I try to run or debug my application on my DE3 board, I get the following error: 

 Using cable "USB-Blaster [USB-0]", device 1, instance 0x01 Processor is already paused Reading System ID at address 0x00023068: verified Initializing CPU cache (if present) OK  Downloading 00000000 ( 0%) Downloaded 9KB in 0.1s   Verifying 00000000 ( 0%) Verify failed between address 0x0 and 0x2223 Leaving target processor paused   I only get this error though, when I connect the jtag_uart. It appears to launch properly (although I don't think it really works correctly), when I disconnect the jtag uart.  My system has 2 processors that share on-chip instruction memory, and then they each have their own on-chip data memory. I don't get any critical warnings in Quartus when I compile. I'm using a DE3 development board.  Any ideas? I've scoured the boards and the usual "verify failed" solutions don't seem to work for me.

[Altera_Forum]

Is your design properly constrained? Have a look at the Timequest report, especially the clocks and unconstrained paths. If the clocks aren't defined properly, then you can have a compile without critical warnings, even if the timing is bad. 

Are you sure the second CPU isn't writing something to the first CPU's instruction memory between the download and verify phases?

[Altera_Forum]

It sounds to me like the two processors are sharing instruction or data memory. If you have initialised any static variables then they'll be in the read/write data section and will be written as the program runs. 

 It's possible that the program on the first CPU is blocked waiting for a host to connect to the JTAG UART.   Check that your read/write and BSS sections are in separate memories or at different addresses

[Altera_Forum]

Although it is a two processor system, I am starting off trying to only run one processor. They share instruction memory but have separate data memories. I don't think this should matter right now though, since only one processor is launching.

[Altera_Forum]

Figured it out! In the SOPC builder, I had disconnected the instruction memory from each of the cpu data master ports. I had assumed that I should just connect the instruction master of each to the instruction memory and the data master of each to their respective data memory - but I guess this isn't the case? Anyways, they are all connected now and specified properly in the system library.

[Altera_Forum]

Yes you need to connect the instruction memory to the CPU's data port whenever you want to be able to upload the application into the instruction memory. This happens usually in two cases:[list][*]when you want to upload an application through JTAG[*]when you use a bootloader that copies the application from flash[/list]And be also careful if the BSP is configured to use some of the instruction memory for data (data, stack, bss or heap).

[Altera_Forum]

To get 'pure' code you'll need: 

 1) A special linker script that assigns readonly data to the data memory (not code memory).  2) Use gcc3 (or rebuild gcc4 with sane options) to remove switch statement jump tables from the text segment.  With a suitable loader it is then possible to run without data access to the instruction memory.