Kernel restart issue while trying to read or write from the address space of hps2fpga and lwhps2fpga

[ManthanWankar]

Currently working on a Arria 10 FPGA and faced this issue while trying to access the gpio connected on the lwhps to fpga bridge but when i try to access the lwhps2fpgs address section(0xff200000) my kernel stucks and restarts.

below i have mentioned the bridge device tree

fpga-bridge@ff200000 {
compatible = “altr,socfpga-lwhps2fpga-bridge”;
reg = <0xff200000 0x00200000>;
resets = <0x06 0x61>;
clocks = <0x08>;
bridge-enable = <0x01>;
altr,l3-syscon = <0x99>;
phandle = <0x5b>;
init_val = <1>;

};

fpga-bridge@c0000000 {
compatible = “altr,socfpga-hps2fpga-bridge”;
reg = <0xc0000000 0x3c000000>;
resets = <0x06 0x60>;
clocks = <0x08>;
bridge-enable = <0x01>;
altr,l3-syscon = <0x99>;
phandle = <0x5c>;
init_val = <1>;
};
been following this guide from rocket board: https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10
and also can any one please share the correct device tree for fpga2hps and fpgs2sdram bridge device tree node

[aikeu]

Hi ManthanWankar,

Can you try to perform bridge enable in Uboot user space before booting into linux kernel?

Thanks.

Regards,

Aik Eu

[ManthanWankar]

have tried that too, also tried to access the registers from uboot , got data  abort error.

the bridges are enable i can see the state of bridge in /sys/class/fpga_bridge/br*/state as enabled

[aikeu]

Hi ManthanWankar,

Is there any error return when execute bridge enable?

If there is no error then when peform md 0xff200000, the system will reset?

Are you using the GSRD from building bootloader to test before any modification?

I can try to test the GSRD on my side but will need some time to do that.

Thanks.

Regards,

Aik Eu

[ManthanWankar]

no error returned while bridge enable

yes it will give a data abort error and the system  will reset.

yes i am using the GSRD only have changed the memory size from 1GB to 2GB else every thing is the same

the default device tree does not have fpga bridges in it's device tree node so have added those.

[ManthanWankar]

also using quartus pro 22.4 instead of quartus pro 23.2

[aikeu]

Hi ManthanWankar,

I was able to execute bridge enable in Uboot user space using GSRD build and can detect the same sys id from the System ID Peripheral Intel FPGA IP which connected to 0xFF200000.

If I didnt perform bridge enable, the system will reset/restart after I execute md 0xFF200000 in Uboot user space.

May I know which device tree file which you change for uboot referring to the link below:

https://github.com/altera-opensource/u-boot-socfpga/tree/socfpga_v2023.01

Is it possible to compare/test with GSRD before any changes being made?

Thanks.

Regards,

Aik Eu

[ManthanWankar]

https://github.com/altera-opensource/u-boot-socfpga/blob/8f4a358cbc616dcc66f6f5c27f402b6a7399f84c/arch/arm/dts/socfpga_arria10_socdk.dtsi#L4

this is the dtsi where i changed the memory size and added bridge definations

[sumanth1]

Hi Aik Eu,

I am also facing the same issue. can please provide   GSRD build procedure with screenshots which  u r following 

[aikeu]

FYI.

Thanks.

Regards,

Aik Eu

[ManthanWankar]

what are your device tree defination for the l3 register look like.

[ManthanWankar]

this is the GSRD qsys and i have added some FPGA led to it 

[ManthanWankar]

and here is the address map

[ManthanWankar]

and can you please share which version of quartus you are using?

[aikeu]

Hi ManthanWankar,

I was following the GSRD from Rocketboards to boot up from QSPI flash. The quartus version I used was the same version(23.2Pro) from Rocketboards building bootloader.

I didnt make any changes to the GSRD/GHRD but only built accordingly and flashed it into the board. I notice you have make some changes to the GHRD and the address for your sysid is different which does not start with offset 0x00000000.(When query with md in Uboot user space, it will be 0xFF200000). Seems like your case will need to query from 0xFF200140, you can try to check on that.

For troubleshooting purpose, I suggest to use the default GSRD/GHR without modification first then bridge enable and query the sys id to verify the bridge is working.

Thanks.

Regards,

Aik Eu

[ManthanWankar]

i cannot use the GSRD as it is because the FPGA part no are different so it will not boot and also i have a custom board with 2GB DDR3 on the HPS side so i have to customize the EMIF also

[ManthanWankar]

also changed the memory reg value from reg = <0x0 0x40000000> to reg = <0x0 0x80000000> in the uboot dtsi

[ManthanWankar]

tried (md 0xff200140), same results the uboot restarts

[aikeu]

Hi ManthanWankar,

Your custom board has only memory size changes, I think can change only the memory size for that in the device tree. The rest remain the same as by default the GSRD has considered the bridge enable functionality.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi ManthanWankar,

Any follow up with the previous comment?

Thanks.

Regards,

Aik Eu

[aikeu]

Hi ManthanWankar,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Thanks.

Regards,

Aik Eu