Re: LE carry chain

Altera_Forum · ‎02-15-2009

I'm trying to implement LE carry chain using low level primitives.

 L_0:LCELL
  PORT MAP (
          in0,out0
  );
  
  D_0:DFFEAS
  PORT MAP(
        d=>out0,
        q=>delay(0),
        clk=>ref_clk,
        ena=>'1',
        clrn=>'1',
        prn=>'1',
        asdata=>'0',
        sclr=>'0',
        sload=>'0',
        aload=>'0'
  );
  
  C_1:CARRY_SUM
  PORT MAP(
        sin=>'0',
        cin=>out0,
        cout=>carry0
  );
  
  L_1:LCELL
  PORT MAP (
        carry0,out1
  );
  
  D_1:DFFEAS
  PORT MAP(
        d=>out1,
        q=>delay(1),
        clk=>ref_clk,
        ena=>'1',
        clrn=>'1',
        prn=>'1',
        asdata=>'0',
        sclr=>'0',
        sload=>'0',
        aload=>'0'
        
  );

I've attached what I receive in RTL Viewer. It's seems like something I want to achieve, but CARRY_SUM primitive is ignored. It's my first contact with primitives so I guest I'm doing something wrong. Particularly I don't know what is sin and sout in CARRY_SUM and how to use it. My intend is to create 64 LE length delay line (and then TDC- time to digital converter). I'll appreciate some help. Device is Cyclone III. I've noticed it should rater be I another forum category, sorry.

Altera_Forum · ‎02-15-2009

1. The RTL apparently belongs to a different VHDL source, cause the instance name of the CARRY_SUM instance is different.

2. Apart from this, it's completely matching the code to my opinion. I don't see, what should be missing.

3. I don't understand, how carry sum is related to logic cell delay line and what you want to achieve with the shown code.

Altera_Forum · ‎02-15-2009

I'm trying to achieve delay chain as shown here:

http://www-ppd.fnal.gov/eedoffice-w/projects/ckm/comadc/wavelettdc_abs08.pdf

(picture 1a)

I'm doing it completely wrong? How would you do it?

edit. Ok, I figured it out. CARRY_SUM documentation should really be better.

Altera_Forum · ‎02-15-2009

I've been yet implementing delay chains in logic cells by applying keep attribute to wire signals, as described e.g. in the stratix cookbook (Advanced Synthesis Cookbook). It's straightforward and works with all FPGA families without considering internal details.

I see, that a TDC design (combination of delay chain and DFFs) could utilize carry chains to achieve a compact structure and (hopefully) small delays. It's most likely possible by device specific WYSWYG LCELL primitives. The cookbook has some Stratix examples with direct definition of carry chains. But I never used this.

I was basically able to place and connect cycloneiii_lcell_comb elements in a design, that have been kept during synthesis. But I don't yet know the binary LUT_MASK coding necessary for a meaningful logic function.

Altera_Forum · ‎02-25-2009

I've got some problem with simulation. In Quartus time simulation it's ok, but in ModelSim there is problem with X values(please take a look at the attachment). It's caused by time volation- example warning from ModelSim:

Warning: */DFFEAS HOLD Low VIOLATION ON DATAIN WITH RESPECT TO CLK;# Expected := 0.084 ns; Observed := 0.074 ns; At : 98.79 ns

I guess that ModelSim is right, but due the nature of this project time volations are natural. You can see that he put's 'X' before and after 1-0 and 0-1 transition. Is there a way to trick ModelSim? I'd like to use testbench simulation.

Altera_Forum · ‎02-25-2009

Yes, ModelSim produces X output for the complete range, that could be possibly affected by a timing violation. This way it marks the result as unknown depending on varying device parameters. In a real device, the result would be determined depending on individual timing parameters, except for a short jitter ruled uncertainty zone, including a certain prohabilty of metastable states.

I'm not aware of a method to change ModelSim behaviour in this regard.

Altera_Forum · ‎12-01-2011

mart_raf, you mentioned you got your design working, what was the problem? I am having the exact same problem as you were having. My carry_sum primitives are being ignored.

Altera_Forum · ‎05-03-2012

same issue, I'm trying to find them using the node locater and can't find them and they don't appear anywhere on the floorplan!!!

Altera_Forum · ‎04-22-2013

Hello,

I am trying to implement a programmable delay using the carry chains. (TDC on FPGA!)

I tried to realize the approach presented in most of the papers. (N Fulladders connected to each other Cout from the previous Adder is the Cin of the subsequent one ) .

The simulation (modelsim) delivers acceptable results but on the hardware it didnt worked properly. I guess that i have to use the dedicated carry chain on the FPGA (cyclone I). Furthermore, I have to keep an eye on Constraints and Timing, but i have never worked with this before.

So, I hope that someone of you have any experience with this topic.

I apprecaite for help.

Regards

Solino

Altera_Forum · ‎04-22-2013

Hi FvM,

I am struggling with a tapped delay line using the carry chain of the FPGA. My intention is to create a delay of 100-150 ps - kind of TDC on FPGA.

But I have several problems concering implementation on my Cyclone I. (see last thread on this page.)

thank you.

bye

Altera_Forum · ‎11-19-2015

Hy guys,

i have your same problem. are you sure that CARRY_SUM is the best primitive to implement a carry chain on FPGA?

thank you

bye bye