LOC Program for VHDL

Altera_Forum · ‎05-20-2012

Hey Guys. I've been asked to count the number of lines of code (LOC) for VHDL. I need to count the physicial lines of code, logical lines of code, and also the number of commented lines.

Anyone have any ideas on an algorithm I can use for this?

Altera_Forum · ‎05-20-2012

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I've been asked to count the number of lines of code (LOC) for VHDL. I need to count the physicial lines of code, logical lines of code, and also the number of commented lines.

Anyone have any ideas on an algorithm I can use for this?

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There is likely a unix tool that already does most of this, eg. awk or sed.

Alternatively write a Perl/Tcl/bash script that parses a file a line at a time, and decides whether the line is a comment, space, or code.

However, distinguishing the lines of VHDL code as being logical might be a little difficult or meaningless, since the following line of code:


c <= a and b;

can also be written as


process(a,b)
begin
      if ((a = '1') and (b = '1')) then
           c <= '1';
      else
           c <= '0';
      end if;
end process;

Ideally you should 'count' the second form as one line of 'logical' code right?

Cheers,

Dave

Altera_Forum · ‎05-21-2012

The limited significance of LLOC measures isn't specific to VHDL. Counting executable statements gives some information about the code's complexity, it can't take account for different levels of verbosity that exist in all programming languages.

Altera_Forum · ‎05-21-2012

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The limited significance of LLOC measures isn't specific to VHDL. Counting executable statements gives some information about the code's complexity, it can't take account for different levels of verbosity that exist in all programming languages.

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Yes, valid point.

The comment:

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I need to count the physicial lines of code, logical lines of code

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led me to write the two code snippets of identical code, as I think this is an example of the type of code that has a different number of physical lines than logic lines.

In this case, could he count the number of lines in the RTL code generated by Quartus after synthesis? Probably not, since there is often a lot of redundant connections in the Altera code (where signals are simply renamed).

Cheers,

Dave

Altera_Forum · ‎05-21-2012

I'm not very familiar with LLOC calculation algorithms, but as a first guess, I would assume 1 for the first and 4 for the second example. Counting terminating ';' may be sufficient.

Logical lines of code aren't related to generated number of machine instructions for a processor or FPGA gate level net lists, I think.